An other Microchip screwup on teh 18F14K22
in [Design]
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From: Spehro Pefhany on 8 May 2010 14:04 On Sat, 08 May 2010 13:01:04 -0500, the renowned "krw(a)att.bizzzzzzzzzzzz" <krw(a)att.bizzzzzzzzzzzz> wrote: >On Sat, 08 May 2010 10:26:59 -0700, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sat, 08 May 2010 15:10:31 GMT, nico(a)puntnl.niks (Nico Coesel) >>wrote: >> >>>John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Fri, 07 May 2010 14:16:26 -0400, Spehro Pefhany >>>><speffSNIP(a)interlogDOTyou.knowwhat> wrote: >>>> >>>>>On Fri, 07 May 2010 09:27:35 -0700, John Larkin >>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>> >>>>>> >>>>>>That's pretty bad. But uPs are getting so complex, so overloaded with >>>>>>features, that the designers are sort of shoveling hunks of home-made >>>>>>or purchased IP into compilers and hoping for the best. And, >>>>>>apparently, not taking much time to simulate and verify. Or document! >>>>>>We had to do a bunch of experiments on the SPI interface on our NXP >>>>>>ARMs; even high-level support people couldn't answer some fundamental >>>>>>timing/framing questions. The SPI and ADC documentation is awful. >>>>>> >>>>>>We use ARM chips that have 30-character pin names, the pin functions >>>>>>are so overloaded. >>>>> >>>>>Who's are you using now? We're getting going with the Luminary parts. >>>> >>>>NXP 80 and 100-pin parts, LPC1758 and LPC1768. We have one 12-channel >>>>4-20 mA thing that has an ARM per floating channel... 13 CPUs on one >>>>VME board. >>>> >>>>What we really want for another project is a faster (500 MHz?) chip >>>>with gigabit ethernet. NXP doesn't have anything quite yet. Marvell >>>>looks good technically but they sort of discourage sub-megapart >>>>customers. Freescale PowerPC looks pretty good. We'll have to decide >>>>soon. >>> >>>Did you look into the IMX series from Freescale? Or the ARM SoCs from >>>Samsung? Very cost effective. >> >>Do any of the Samsungs have GbE? I'll have my guys look into them. >> >>Marvell is coming around, after some pressure from the distributor and >>a lucky contact at the Embedded System Conference. But their eval >>board is $4K, presumably mostly earnest money. > >$4K?! They really don't want business. I remember when the Asian chip makers wanted $20K for a development system (and 50,000 pieces as the rock-bottom minimum order). That was back when $20K would buy several new cars.. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff(a)interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
From: krw on 8 May 2010 14:18 On Sat, 08 May 2010 14:04:20 -0400, Spehro Pefhany <speffSNIP(a)interlogDOTyou.knowwhat> wrote: >On Sat, 08 May 2010 13:01:04 -0500, the renowned >"krw(a)att.bizzzzzzzzzzzz" <krw(a)att.bizzzzzzzzzzzz> wrote: > >>On Sat, 08 May 2010 10:26:59 -0700, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 08 May 2010 15:10:31 GMT, nico(a)puntnl.niks (Nico Coesel) >>>wrote: >>> >>>>John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>>On Fri, 07 May 2010 14:16:26 -0400, Spehro Pefhany >>>>><speffSNIP(a)interlogDOTyou.knowwhat> wrote: >>>>> >>>>>>On Fri, 07 May 2010 09:27:35 -0700, John Larkin >>>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>>> >>>>>>> >>>>>>>That's pretty bad. But uPs are getting so complex, so overloaded with >>>>>>>features, that the designers are sort of shoveling hunks of home-made >>>>>>>or purchased IP into compilers and hoping for the best. And, >>>>>>>apparently, not taking much time to simulate and verify. Or document! >>>>>>>We had to do a bunch of experiments on the SPI interface on our NXP >>>>>>>ARMs; even high-level support people couldn't answer some fundamental >>>>>>>timing/framing questions. The SPI and ADC documentation is awful. >>>>>>> >>>>>>>We use ARM chips that have 30-character pin names, the pin functions >>>>>>>are so overloaded. >>>>>> >>>>>>Who's are you using now? We're getting going with the Luminary parts. >>>>> >>>>>NXP 80 and 100-pin parts, LPC1758 and LPC1768. We have one 12-channel >>>>>4-20 mA thing that has an ARM per floating channel... 13 CPUs on one >>>>>VME board. >>>>> >>>>>What we really want for another project is a faster (500 MHz?) chip >>>>>with gigabit ethernet. NXP doesn't have anything quite yet. Marvell >>>>>looks good technically but they sort of discourage sub-megapart >>>>>customers. Freescale PowerPC looks pretty good. We'll have to decide >>>>>soon. >>>> >>>>Did you look into the IMX series from Freescale? Or the ARM SoCs from >>>>Samsung? Very cost effective. >>> >>>Do any of the Samsungs have GbE? I'll have my guys look into them. >>> >>>Marvell is coming around, after some pressure from the distributor and >>>a lucky contact at the Embedded System Conference. But their eval >>>board is $4K, presumably mostly earnest money. >> >>$4K?! They really don't want business. > >I remember when the Asian chip makers wanted $20K for a development >system (and 50,000 pieces as the rock-bottom minimum order). That was >back when $20K would buy several new cars.. Sure, we used to buy Intel, Tek, and HP development systems that went higher than that. A lot of things have changed in the last 30 years. Everyone who wants business now gives this stuff away. I have to refuse a lot of dev kits that I know I'll never have the time to even play with. At the *most* these dev kits are couple of hundred bucks, complete with what used to be a few thousand bucks worth of software and licenses thrown in (I tell the Altera sales guy all about the new Spartan 6 features ;-).
From: Nico Coesel on 8 May 2010 15:37 John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sat, 08 May 2010 15:10:31 GMT, nico(a)puntnl.niks (Nico Coesel) >wrote: > >>John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Fri, 07 May 2010 14:16:26 -0400, Spehro Pefhany >>><speffSNIP(a)interlogDOTyou.knowwhat> wrote: >>> >>>>On Fri, 07 May 2010 09:27:35 -0700, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>> >>>>>That's pretty bad. But uPs are getting so complex, so overloaded with >>>>>features, that the designers are sort of shoveling hunks of home-made >>>>>or purchased IP into compilers and hoping for the best. And, >>>>>apparently, not taking much time to simulate and verify. Or document! >>>>>We had to do a bunch of experiments on the SPI interface on our NXP >>>>>ARMs; even high-level support people couldn't answer some fundamental >>>>>timing/framing questions. The SPI and ADC documentation is awful. >>>>> >>>>>We use ARM chips that have 30-character pin names, the pin functions >>>>>are so overloaded. >>>> >>>>Who's are you using now? We're getting going with the Luminary parts. >>> >>>NXP 80 and 100-pin parts, LPC1758 and LPC1768. We have one 12-channel >>>4-20 mA thing that has an ARM per floating channel... 13 CPUs on one >>>VME board. >>> >>>What we really want for another project is a faster (500 MHz?) chip >>>with gigabit ethernet. NXP doesn't have anything quite yet. Marvell >>>looks good technically but they sort of discourage sub-megapart >>>customers. Freescale PowerPC looks pretty good. We'll have to decide >>>soon. >> >>Did you look into the IMX series from Freescale? Or the ARM SoCs from >>Samsung? Very cost effective. > >Do any of the Samsungs have GbE? I'll have my guys look into them. The Samsungs have no internal MAC so you can attach any MAC-PHY you want. There are very few SoCs with GbE. >Marvell is coming around, after some pressure from the distributor and >a lucky contact at the Embedded System Conference. But their eval >board is $4K, presumably mostly earnest money. Way too expensive. Select a SoC for which $200 eval boards are available so you know you'll have some community support. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico(a)nctdevpuntnl (punt=.) --------------------------------------------------------------
From: Joel Koltner on 9 May 2010 18:26 "Jan Panteltje" <pNaonStpealmtje(a)yahoo.com> wrote in message news:hs3ioh$tr7$1(a)news.albasani.net... > Do you not think it is strange that it took 8 revisions for it to work (IF > it works in A8)? Seems like it's not that uncommon anymore. > What does a new mask cost these days? Must be very expensive, especially > if after 7 silicon versions with the same problem not a single customer will > buy these chips. It's apparently not expensive relative to the predicted lost sales of delaying the part by, e.g., a year. :-( Unfortunately it's very unlikely that the bugs in your 18F14K22 would have stopped anyone who was planning to buy a million of the things per year from continuing to use the part... > When I bought the Z80, in the 19 eighties, a chip that has a much > more complicated instruction set, but much easier to use, it worked on all > advertised issues. I don't know if Microchip is doing it yet, but many microcontrollers today are designed in Verilog or VHDL, and this seems to have brought with it the mindset of "all designs have bugs" that permeates the software industry today. (Note that an x86-compatible CPU today from AMD or Intel often has dozens or even hundreds of errata... also note that for years now Intel and AMD have make some of their CPUs "soft" so that microcode updates applied at boot by the BIOS can fix some of the problems...) ---Joel
From: JosephKK on 9 May 2010 19:06
On Fri, 07 May 2010 17:57:31 -0500, "krw(a)att.bizzzzzzzzzzzz" <krw(a)att.bizzzzzzzzzzzz> wrote: >On Fri, 07 May 2010 14:16:26 -0400, Spehro Pefhany ><speffSNIP(a)interlogDOTyou.knowwhat> wrote: > >>On Fri, 07 May 2010 09:27:35 -0700, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>> >>>That's pretty bad. But uPs are getting so complex, so overloaded with >>>features, that the designers are sort of shoveling hunks of home-made >>>or purchased IP into compilers and hoping for the best. And, >>>apparently, not taking much time to simulate and verify. Or document! >>>We had to do a bunch of experiments on the SPI interface on our NXP >>>ARMs; even high-level support people couldn't answer some fundamental >>>timing/framing questions. The SPI and ADC documentation is awful. >>> >>>We use ARM chips that have 30-character pin names, the pin functions >>>are so overloaded. >> >>Who's are you using now? We're getting going with the Luminary parts. >> >>>What would be nice would be if things like SPI were small RAM-driven >>>microengines. Then the functionality would be in loadable code, not >>>hard-wired silicon. Sort of like Motorola's TPU blocks. They could be >>>repurposed, too. >>> >>>John >> >>You'd think it would be relatively simple to put a thin FPGA or CPLD >>fabric around the core, perhaps preloaded from ROM with some useful >>defaults. > >That's a lot easier said than done. First, X, A, and A have most of the IP >locked up for FPGA sorts of things. Second, the development software for such >things is non-trivial. Great idea, but not likely to fly. PALs and small FPGAs have been around over 30 years. If you limit to not much more tech, all the patents should be expired. Atmel, Freescale, Microchip, etc., all have nice multiplexing tech for the multifunction pins. |