Antti....
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From: Nial Stewart on 2 Mar 2010 09:17 I've just noticed and read the thread you started just before Christmas about your Fifo problem. You said... > problem fixed! > solution and explanation in the next Brain issue > (I will post short post also after the issue release) Any sign of the new Brain? BTW, was the read indicated by a single clock width pulse that was always de-asserted after each read, or could this have been active for a number of 62.5mhz cycles? I'd have changed the design so the internal read flag was inverted at each read, then the number of reads couldn't have been mistaken by the higher speed clock domain. Looking forward to the solution.. Nial
From: Antti on 4 Mar 2010 13:54 On Mar 2, 4:17 pm, "Nial Stewart" <nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote: > I've just noticed and read the thread you started just before Christmas > about your Fifo problem. > > You said... > > > problem fixed! > > solution and explanation in the next Brain issue > > (I will post short post also after the issue release) > > Any sign of the new Brain? > > BTW, was the read indicated by a single clock width pulse that was always > de-asserted after each read, or could this have been active for a number > of 62.5mhz cycles? > > I'd have changed the design so the internal read flag was inverted at > each read, then the number of reads couldn't have been mistaken by the > higher speed clock domain. > > Looking forward to the solution.. > > Nial sign :)! just returned from embedded still needing some breathe time FIFO proble solution: this was SO STUPID, the reason was that the engineer who made the "read enable" signal from the PPC user logic for some mystical reason did move this read enable from the PPC clock domain to the MGT clock domain that was in sync with the master clock on the master board, so in the slave board all was fine, except fifo read enable was in the clock domain of the master (syncronised to the MGT recovered clock) this also explains why the problem was not visible in chipscope: chipscope did latch the signal in 1 F/F and no bad disaster happened, what I also witnessed, but in the FIFO itself the clock enable was controlling multiple F/F that occasionally did then go nuts what I also witnessed. so there was no clock issue, no FIFO issue, but.. well things happen. I was not the only person who did look at the code, but nobody did see any issue, well we all mostly looked at the problems with the FIFO and CLOCK signals... Antti
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