Anyone else need bigger parts in small (low pin count) packages
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From: Michael Kellett on 29 May 2010 04:57 "Symon" <symon_brewer(a)hotmail.com> wrote in message news:htpkq7$435$1(a)news.eternal-september.org... > You can't meet the SI requirements of modern sub-ns rise time silicon's > I/O in 'easy to solder' packages. It's because of the loop area. > > BGAs "are harder to probe" made me laugh! I bet you still have a logic > analyser! > > One way to prevent yourself becoming an extinct dinosaur is to splash the > cash on some decent stimulation tools. Your competitors have. > > Syms. Lighten up Syms ! For serious work with hardware I need a logic analyser and a scope !! (if you can suggest a "stimulation tool" substitute I'm listening). I'm totally with Rick on this one - TQFP easy to hand solder, easy to probe, check, modify etc. Most of my designs are one or two off, weirdo interfaces for production line test systems - the largest production run I've ever done with an FPGA was about 100 off. I can see the appeal of BGA for mass production but I'm convinced that TQFP is cheaper to prototype in low pin counts. A serious FPGA (>20K LUT) in 100 pin TQFP would be very nice. But I accept that the number I might buy wouldn't make the supplier very rich. Michael Kellett
From: Nico Coesel on 29 May 2010 06:40 Rob Gaddi <rgaddi(a)technologyhighland.com> wrote: >On 5/28/2010 10:05 AM, rickman wrote: >> I am looking at reducing the cost of a board while improving the >> performance and one way is to add a processor to offload the low >> bandwidth portions of an FPGA design and then reduce the capacity of >> the FPGA. Using an FPGA with 5 volt tolerant I/Os will let me remove >> a couple of quick switch parts as well. This has potential of saving >> a few bucks off the top and greatly improving the usable capacity of >> the device. However... there just don't seem to be *any* FPGAs that >> fit the bill. >> >> 5 volt tolerance (a potential bonus, but not required) >> small package/low pin count, not BGA, ~32 usable I/Os, 48 TQFP ideal >> 500 LUTs and 256 bits of memory >> Price<$5 >> >> Currently the entire design is in a Lattice XP device with 3k LUTs, >> but is 90% utilized with a recent capability upgrade. I can't even go >> with a larger FPGA without also going to a BGA package which drives >> the price up. I don't like BGAs because they take extra space for >> fanout of the signals and they are harder to probe than QFPs. I don't >> think any two of these three requirements can be found in the same >> part. Well, maybe CPLDs come in smaller packages at a low cost... >> >> I'm just surprised that there isn't more demand for FPGAs in low pin >> count packages. I guess I'm getting to be a dinosaur in my preference >> for QFPs. Still, I don't think you can even find a FPGA under $10 in >> a BGA package because the pin count is typically higher which drives >> the part cost up. >> >> Just some thoughts about my continued frustration in reaching design >> goals. >> >> Rick > >My problem with QFPs is that those long leads on 0.5mm pitch are perfect >solder wicks. Our BGA soldering yield is 100%, whereas we have to clear >at least one bridge on QFPs about half the time. Sounds more like a soldering process problem than a package problem. We use a lot of QFP packages for many different devices and we never see solder bridging problems. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico(a)nctdevpuntnl (punt=.) --------------------------------------------------------------
From: Symon on 29 May 2010 20:22 On 5/29/2010 9:57 AM, Michael Kellett wrote: > "Symon"<symon_brewer(a)hotmail.com> wrote in message > news:htpkq7$435$1(a)news.eternal-september.org... >> You can't meet the SI requirements of modern sub-ns rise time silicon's >> I/O in 'easy to solder' packages. It's because of the loop area. >> >> BGAs "are harder to probe" made me laugh! I bet you still have a logic >> analyser! >> >> One way to prevent yourself becoming an extinct dinosaur is to splash the >> cash on some decent stimulation tools. Your competitors have. >> >> Syms. > Lighten up Syms ! > > For serious work with hardware I need a logic analyser and a scope !! (if > you can suggest a "stimulation tool" substitute I'm listening). > > I'm totally with Rick on this one - TQFP easy to hand solder, easy to probe, > check, modify etc. > Most of my designs are one or two off, weirdo interfaces for production line > test systems - the largest production run I've ever done with an FPGA was > about 100 off. > > I can see the appeal of BGA for mass production but I'm convinced that TQFP > is cheaper to prototype in low pin counts. A serious FPGA (>20K LUT) in 100 > pin TQFP would be very nice. > But I accept that the number I might buy wouldn't make the supplier very > rich. > > Michael Kellett > Hi Michael, Lighten up? About FPGA design? OK, I'll try! Anyway, it made me laugh, how light do you want? And then you talk about serious work. Talk about bringing the mood down! :-) Anyway, I have a 'scope too. I use it a fair bit, but not as much as LTSpice. I don't have a logic analyser. I have used Chipscope as a last resort, but a simulator like ModelSIM is my preferred tool for catching logic bugs. My spectrum analyser is far more useful than a logic analyser could be. Here's the skinny. You're correct that TQFPs are easier to hand solder than BGAs. Also, they are easier to probe. That's just as well because the SI of a TQFP because of the leads' loop area is poor enough that you may well need to probe them. I would have thought that the kind of ATE type equipment you are making needs to have good SI? When I design test equipment, I would not even consider a leaded part. Especially as, in a pinch, you can reflow a BGA with a toaster oven. Anyway, I don't know your specific circumstances, and I'm sure you have excellent reasons for choosing the parts you do. I would just like to point out that there are some jolly good incentives for ditching leaded parts, and that some investment in decent simulation tools and a toaster oven is the way forward! Cheers, Syms.
From: John Adair on 31 May 2010 03:44 I'd agree on the comment on solder bridges. We have a rework of about 0.03% on our BGAs last year. Our TSSOP/TQFP rework rate is something like 100x that. BGAs do get a little tricky when you go down to 0.5mm pitch like we do on our Craignell1 family but 0.8mm and 1mm pitch are easy. The minimum board technology gets more expensive in low volumes although this becomes much less of an issue if you start making 1k+ units. The TQFP I would agree with is that signal integrity is much worse that BGAs typically. Ground bounce effects can be very bad. We have seen customer designs where they had lots of problems when they have used a 2 layer PCB and a TQFP package together. That's not say it can't be done. As yet we have not had any problems on our Polmaddie boards reported and they areTQFP on a 2 layer board. We spent lots of time looking at how we could solve those issues before they happened on these boards and it looks like it paid off. John Adair Enterpoint Ltd. On 28 May, 18:29, Rob Gaddi <rga...(a)technologyhighland.com> wrote: > On 5/28/2010 10:05 AM, rickman wrote: > > > > > > > I am looking at reducing the cost of a board while improving the > > performance and one way is to add a processor to offload the low > > bandwidth portions of an FPGA design and then reduce the capacity of > > the FPGA. Using an FPGA with 5 volt tolerant I/Os will let me remove > > a couple of quick switch parts as well. This has potential of saving > > a few bucks off the top and greatly improving the usable capacity of > > the device. However... there just don't seem to be *any* FPGAs that > > fit the bill. > > > 5 volt tolerance (a potential bonus, but not required) > > small package/low pin count, not BGA, ~32 usable I/Os, 48 TQFP ideal > > 500 LUTs and 256 bits of memory > > Price<$5 > > > Currently the entire design is in a Lattice XP device with 3k LUTs, > > but is 90% utilized with a recent capability upgrade. I can't even go > > with a larger FPGA without also going to a BGA package which drives > > the price up. I don't like BGAs because they take extra space for > > fanout of the signals and they are harder to probe than QFPs. I don't > > think any two of these three requirements can be found in the same > > part. Well, maybe CPLDs come in smaller packages at a low cost... > > > I'm just surprised that there isn't more demand for FPGAs in low pin > > count packages. I guess I'm getting to be a dinosaur in my preference > > for QFPs. Still, I don't think you can even find a FPGA under $10 in > > a BGA package because the pin count is typically higher which drives > > the part cost up. > > > Just some thoughts about my continued frustration in reaching design > > goals. > > > Rick > > My problem with QFPs is that those long leads on 0.5mm pitch are perfect > solder wicks. Our BGA soldering yield is 100%, whereas we have to clear > at least one bridge on QFPs about half the time. > > I'd love a 49 ball, 1mm pitch part. With 6/6 rules you could route out > all but the inner 9 balls on the top layer; with 5/5 you could route out > all but the center (which in a sensible world would be ground anyhow). > That would put it at about 8mm on a side while still providing enough IO > pins to do something interesting. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order- Hide quoted text - > > - Show quoted text -
From: Rob Gaddi on 1 Jun 2010 11:58
On 5/29/2010 5:22 PM, Symon wrote: > On 5/29/2010 9:57 AM, Michael Kellett wrote: >> "Symon"<symon_brewer(a)hotmail.com> wrote in message >> news:htpkq7$435$1(a)news.eternal-september.org... >>> You can't meet the SI requirements of modern sub-ns rise time silicon's >>> I/O in 'easy to solder' packages. It's because of the loop area. >>> >>> BGAs "are harder to probe" made me laugh! I bet you still have a logic >>> analyser! >>> >>> One way to prevent yourself becoming an extinct dinosaur is to splash >>> the >>> cash on some decent stimulation tools. Your competitors have. >>> >>> Syms. >> Lighten up Syms ! >> >> For serious work with hardware I need a logic analyser and a scope !! (if >> you can suggest a "stimulation tool" substitute I'm listening). >> >> I'm totally with Rick on this one - TQFP easy to hand solder, easy to >> probe, >> check, modify etc. >> Most of my designs are one or two off, weirdo interfaces for >> production line >> test systems - the largest production run I've ever done with an FPGA was >> about 100 off. >> >> I can see the appeal of BGA for mass production but I'm convinced that >> TQFP >> is cheaper to prototype in low pin counts. A serious FPGA (>20K LUT) >> in 100 >> pin TQFP would be very nice. >> But I accept that the number I might buy wouldn't make the supplier very >> rich. >> >> Michael Kellett >> > Hi Michael, > > Lighten up? About FPGA design? OK, I'll try! Anyway, it made me laugh, > how light do you want? And then you talk about serious work. Talk about > bringing the mood down! :-) > > Anyway, I have a 'scope too. I use it a fair bit, but not as much as > LTSpice. I don't have a logic analyser. I have used Chipscope as a last > resort, but a simulator like ModelSIM is my preferred tool for catching > logic bugs. My spectrum analyser is far more useful than a logic > analyser could be. > > Here's the skinny. You're correct that TQFPs are easier to hand solder > than BGAs. Also, they are easier to probe. That's just as well because > the SI of a TQFP because of the leads' loop area is poor enough that you > may well need to probe them. I would have thought that the kind of ATE > type equipment you are making needs to have good SI? When I design test > equipment, I would not even consider a leaded part. Especially as, in a > pinch, you can reflow a BGA with a toaster oven. > > Anyway, I don't know your specific circumstances, and I'm sure you have > excellent reasons for choosing the parts you do. I would just like to > point out that there are some jolly good incentives for ditching leaded > parts, and that some investment in decent simulation tools and a toaster > oven is the way forward! > > Cheers, Syms. > The logic analyzer's not because you don't understand what your FPGA is doing. The logic analyzer's because you don't understand what the complex ASSP your FPGA is hooked up to is doing, because the data sheet is both 800 pages long and woefully incomplete. And so you take your best guess at how it behaves, throw together a simulation model of it, and crank out your logic, but then you put it on the copper and use the LA to find out that you vastly misunderstood the bus interface because the translation from Japanese to English by way of Sanskrit wasn't clear. Simulate, but verify. -- Rob Gaddi, Highland Technology Email address is currently out of order |