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From: rickman on 28 May 2010 13:05
I am looking at reducing the cost of a board while improving the
performance and one way is to add a processor to offload the low
bandwidth portions of an FPGA design and then reduce the capacity of
the FPGA. Using an FPGA with 5 volt tolerant I/Os will let me remove
a couple of quick switch parts as well. This has potential of saving
a few bucks off the top and greatly improving the usable capacity of
the device. However... there just don't seem to be *any* FPGAs that
fit the bill.

5 volt tolerance (a potential bonus, but not required)
small package/low pin count, not BGA, ~32 usable I/Os, 48 TQFP ideal
500 LUTs and 256 bits of memory
Price <$5

Currently the entire design is in a Lattice XP device with 3k LUTs,
but is 90% utilized with a recent capability upgrade. I can't even go
with a larger FPGA without also going to a BGA package which drives
the price up. I don't like BGAs because they take extra space for
fanout of the signals and they are harder to probe than QFPs. I don't
think any two of these three requirements can be found in the same
part. Well, maybe CPLDs come in smaller packages at a low cost...

I'm just surprised that there isn't more demand for FPGAs in low pin
count packages. I guess I'm getting to be a dinosaur in my preference
for QFPs. Still, I don't think you can even find a FPGA under $10 in
a BGA package because the pin count is typically higher which drives
the part cost up.

Just some thoughts about my continued frustration in reaching design
goals.

Rick
From: Rob Gaddi on 28 May 2010 13:29
On 5/28/2010 10:05 AM, rickman wrote:
> I am looking at reducing the cost of a board while improving the
> performance and one way is to add a processor to offload the low
> bandwidth portions of an FPGA design and then reduce the capacity of
> the FPGA. Using an FPGA with 5 volt tolerant I/Os will let me remove
> a couple of quick switch parts as well. This has potential of saving
> a few bucks off the top and greatly improving the usable capacity of
> the device. However... there just don't seem to be *any* FPGAs that
> fit the bill.
>
> 5 volt tolerance (a potential bonus, but not required)
> small package/low pin count, not BGA, ~32 usable I/Os, 48 TQFP ideal
> 500 LUTs and 256 bits of memory
> Price<$5
>
> Currently the entire design is in a Lattice XP device with 3k LUTs,
> but is 90% utilized with a recent capability upgrade. I can't even go
> with a larger FPGA without also going to a BGA package which drives
> the price up. I don't like BGAs because they take extra space for
> fanout of the signals and they are harder to probe than QFPs. I don't
> think any two of these three requirements can be found in the same
> part. Well, maybe CPLDs come in smaller packages at a low cost...
>
> I'm just surprised that there isn't more demand for FPGAs in low pin
> count packages. I guess I'm getting to be a dinosaur in my preference
> for QFPs. Still, I don't think you can even find a FPGA under $10 in
> a BGA package because the pin count is typically higher which drives
> the part cost up.
>
> Just some thoughts about my continued frustration in reaching design
> goals.
>
> Rick

My problem with QFPs is that those long leads on 0.5mm pitch are perfect
solder wicks. Our BGA soldering yield is 100%, whereas we have to clear
at least one bridge on QFPs about half the time.

I'd love a 49 ball, 1mm pitch part. With 6/6 rules you could route out
all but the inner 9 balls on the top layer; with 5/5 you could route out
all but the center (which in a sensible world would be ground anyhow).
That would put it at about 8mm on a side while still providing enough IO
pins to do something interesting.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
From: Uwe Bonnes on 28 May 2010 15:23
Rob Gaddi <rgaddi(a)technologyhighland.com> wrote:

> My problem with QFPs is that those long leads on 0.5mm pitch are perfect
> solder wicks. Our BGA soldering yield is 100%, whereas we have to clear
> at least one bridge on QFPs about half the time.

> I'd love a 49 ball, 1mm pitch part. With 6/6 rules you could route out
> all but the inner 9 balls on the top layer; with 5/5 you could route out
> all but the center (which in a sensible world would be ground anyhow).
> That would put it at about 8mm on a side while still providing enough IO
> pins to do something interesting.

Some spare rows between the center supply and the IO pins on the outer rows
could also make a two layer enabled BGA package.

Otherwise the XC3S50A-VQ100 with a small SPI flash could could be what the
original poster asked for...
--
Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: rickman on 28 May 2010 16:37
On May 28, 3:23 pm, Uwe Bonnes <b...(a)elektron.ikp.physik.tu-
darmstadt.de> wrote:
> Rob Gaddi <rga...(a)technologyhighland.com> wrote:
> > My problem with QFPs is that those long leads on 0.5mm pitch are perfect
> > solder wicks.  Our BGA soldering yield is 100%, whereas we have to clear
> > at least one bridge on QFPs about half the time.
> > I'd love a 49 ball, 1mm pitch part.  With 6/6 rules you could route out
> > all but the inner 9 balls on the top layer; with 5/5 you could route out
> > all but the center (which in a sensible world would be ground anyhow).
> > That would put it at about 8mm on a side while still providing enough IO
> > pins to do something interesting.
>
> Some spare rows between the center supply and the IO pins on the outer rows
> could also make a two layer enabled BGA package.
>
> Otherwise the XC3S50A-VQ100 with a small SPI flash could could be what the
> original poster asked for...

Hi Uwe,

I have seen the Xilinx parts and they don't do much for me. Compared
to what I am using now, the 3S50 is less than half the size at only
1400 LUTs while the 3S200 is only slightly larger at 3600 LUTs vs 3000
LUTs. The 3S200 is not any cheaper and uses more board space with the
SPI flash as well as costing more. I am trying to make the same board
cheaper and have *no* extra space on the board. So to add an MCU, I
need to reduce the size of the FPGA. I would love to ditch the FPGA
and go 100% software, but there is one interface that makes that
impossible I think. The app configuration data (not FPGA
configuration) comes over a serial port that has timing requirements
for read that you can't meet with software. So a small ram block has
to be written and read in some sort of PLD. That is why I can't use
most of the CPLDs on the market.

Cypress has a configurable CPU out, but their analog is not too good
and the digital is not very programmable. The Actel FPGA with a CPU
is way too expensive at $40. Currently the CODEC used is $2 and the
FPGA is under $10 in a TQ100 package (flash based so no external
flash). I just can't seem to beat this combination either in price or
board space. The only thing I can do is to put a CPU into the FPGA
which is an option I have been considering for a while. I just would
prefer to use a standard MCU which would give me a lot more memory
than the 6 kB currently available, but they just don't make an FPGA
which will fit this design.

Rick
From: Symon on 28 May 2010 19:49
You can't meet the SI requirements of modern sub-ns rise time silicon's
I/O in 'easy to solder' packages. It's because of the loop area.

BGAs "are harder to probe" made me laugh! I bet you still have a logic
analyser!

One way to prevent yourself becoming an extinct dinosaur is to splash
the cash on some decent stimulation tools. Your competitors have.

Syms.
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