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From: nobody on 7 Sep 2009 21:34
After programming an FPGA, XC3S250EVQ100, via Slave Parallel through
an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize
data and fpga_cclk into the FPGA the done pin goes high. The problem I
am having is the bidirectional does not release and allow the FPGA to
drive the data bus to CPLD and then finally into an external 8 LED
bank. I am fairly confident that the FPGA is loaded correctly with the
bin file, by accident I reprogrammed the CPLD releasing the bus the
FPGA, having been programmed, drove the bidirectional data bus and the
lit the 8 LED bank appropriately. Any help on this issues would be
apprciated, thank you. CODE:


----------------------------------------------------------------------------------
-- Company: Electronic Realization L.L.C.
-- Engineer: Cy Drollinger
-- Create Date: 10:44:37 07/08/2009
-- Design Name: USB/FPGA Spartan3E Develpoement
-- Module Name: CPLD - Behavioral
-- Project Name:
-- Target Devices: XC2C64A VQ100
-- Tool versions:
-- Description:
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity CPLD is
Port ( --CPLD LOCATIONS
--Master clock oscillator 50 MHz CTS - CB3
mclk : in STD_LOGIC; --pin 22
mclk_ce : out STD_LOGIC; --pin 70 Logic

--Xilinx Spartan 3E VQ100 mode and variant
Variant : out STD_LOGIC_VECTOR (2 downto 0); --pin 34, 33, 30
Mode : out STD_LOGIC_VECTOR (2 downto 0); --pin 42, 39, 36

--Xilinx Spartan 3E VQ100
FPGA_MOSI : out STD_LOGIC; --pin 90 this is also CSI_B
FPGA_BUSY : in STD_LOGIC; --pin 91 if clk is less than 50 MHz
FPGA_INITB : in STD_LOGIC; --pin 92
FPGA_CSO_B : inout STD_LOGIC; --pin 94
FPGA_cclk : out STD_LOGIC:='0'; --pin 27
FPGA_done : inout STD_LOGIC; --pin 28
FPGA_prog_B: inout STD_LOGIC; --pin 99
FPGA_HSWAP: out STD_LOGIC; --pin 24
FPGA_D: inout STD_LOGIC_VECTOR(7 downto 0); --pin 89 81 79 78 77
41 40 35

--Numonyx M25P16
SPI_flash_HOLD : out STD_LOGIC; --pin 76 SPI '1'
SPI_flash_W : out STD_LOGIC; --pin 97 SPI '1'

--FTDI FT245RL USB to parallel output
usb_pwren : inout STD_LOGIC; --pin 43
usb_wr : in STD_LOGIC; --pin 49
usb_rd : inout STD_LOGIC; --pin 50
data : inout STD_LOGIC_VECTOR (7 downto 0); --pin 56 53 55 61 52
60 58 64
usb_tx : in STD_LOGIC; --pin 67
usb_rx : in STD_LOGIC; --pin 68 when low data ready
usb_rst : inout STD_LOGIC; --pin 14

--User I/O
LEDs : out STD_LOGIC_VECTOR (8 downto 1); --pin 1-4 and 6-9
SW : inout STD_LOGIC_VECTOR (2 downto 0)); --pin 71, 72, 74 need
to be

end CPLD;

architecture Behavioral of CPLD is

--FPGA Configuration

signal SW_0_hi :std_logic; --CPLD is in a all I/O pullups
signal SW_1_hi :std_logic; --CPLD is in a all I/O pullups
signal SW_2_hi :std_logic; --CPLD is in a all I/O pullups
Signal fpga_timing : integer range 0 to 256 :=0;
Signal bidir_bus :std_logic_vector (7 downto 0);
Signal bidir_reg :std_logic_vector (7 downto 0);
Signal done :std_logic;
--FTDI USB chip overhead

signal usb_dry :std_logic; --signal is a synchronized
signal previous_usb_dry :std_logic; --signal is the value of
signal previous :std_logic;
Signal usb_timing : integer range 0 to 256 :=4;

BEGIN

--------------------------------------------------------------------------------------------------------------------------------------
-- Author : Cy Drollinger
-- Date : 7-16-09
-- Description : synchronizing asynchronous inpoputs usb data ready
line(sub_rx), SW(0), SW(1), and SW(2)
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
--HARDWARE SYSTEM ON PCB --TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Synchronize_inputs: process(mclk)
begin
if rising_edge(mclk) then
if usb_rx = '0' then -- RXF# is an active
usb_dry <= '1';
else
usb_dry <= '0';
end if;
previous <= usb_dry;
previous_usb_dry <= previous;
if SW(0) = '1' then
SW_0_hi <= '1';
else
SW_0_hi <= '0';
end if;
if SW(1) = '1' then
SW_1_hi <= '1';
else
SW_1_hi <= '0';
end if;
if SW(2) <= '1' then
SW_2_hi <= '1';
else
SW_2_hi <= '0';
end if;
end if;
end process;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author : Cy Drollinger
-- Date : 7-16-09
-- Description : Upon SW(1) going low the FGPA_prog_b pulses (ONE
SHOT) high for two mclks.
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
--HARDWARE SYSTEM ON PCB --TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Pulse_Prog_B: process (mclk) --
begin
if rising_edge(mclk) then
if SW_1_hi = '0' and FPGA_timing < 22 then
FPGA_timing <= FPGA_timing + 1;
if fpga_timing > 0 and fpga_timing < 21 then
fpga_prog_b <= '0';
else
fpga_prog_b <= '1'; -- fpga_prog_b held low for
end if;
else if SW_1_hi = '1' then
fpga_timing <= 0;
end if;
end if;
end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author : Cy Drollinger
-- Date : 7-16-09
-- Description : providing timing for usb_rd through usb_data_rdy Data
sheet DSFT245R1 pg. 12 fifo read
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
--HARDWARE SYSTEM ON PCB --TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Load_FPGA_Slave_Parallel: process(mclk) --
begin
if rising_edge(mclk) then
if usb_dry = '1' and previous_usb_dry ='0' and fpga_initb = '1'
then
usb_timing <= 0;
elsif usb_timing < 5 then
usb_timing <= usb_timing + 1;
end if;
case usb_timing is
when 0 =>
usb_rd <='0';
when 1 =>
usb_rd <='0';
when 2 =>
usb_rd <='0';
when 3 =>
usb_rd <='0';
fpga_cclk <= '1';
when 4 =>
usb_rd <='1';
fpga_cclk <= '0';
when others =>
end case;
end if;
end process;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author : unknown
-- Date : 9-7-09
-- Description : LED MUX between initial programming of FPGA and data
out of FPGA
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
--HARDWARE SYSTEM ON PCB --TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Bidirectional_FF: PROCESS(mclk)
BEGIN
IF rising_edge(mclk) THEN -- Creates the flipflops
bidir_reg <= data;
LEDs <= not(bidir_bus);
END IF;
END PROCESS;


Bidirectional_Bus PROCESS (FPGA_done, FPGA_d) --
Behavioral representation
BEGIN -- of tri-states.
IF FPGA_done = '1' THEN
FPGA_d <= "ZZZZZZZZ";
bidir_bus <= FPGA_d;
ELSE
FPGA_d <= bidir_reg;
bidir_bus <= FPGA_d;
END IF;
END PROCESS;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author : Cy Drollinger
-- Date : 6-18-09
-- Description : Hardwiring the CPLD for the board configuration of
the usb and fpga
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
--HARDWARE SYSTEM ON PCB --TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
--Master clock oscillator 50 MHz CTS - CB3
mclk_ce <= '1'; --enables the 50 MHz
-- Xilinx Spartan 3E VQ100 mode and variant
Mode <= "110"; --mode Slave Parallel
--Xilinx Spartan 3E Slave Parallel
fpga_mosi <= '0';
--FTDI USB PARALLEL
usb_rst <= SW_0_hi;
end Behavioral;

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