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From: wdeninger on 7 Sep 2009 18:37
Hello,

I've run into a problem bit bang loading (Slave serial) the Spartan 3
from an MCU. The Spartan 3 is setup with M0,M1 & M2 tied high
(verified). I can verify the active CCLK and DIN during programming,
and I can see transitional changes to INIT_L and DONE during
programming.

I follow the instructions at http://www.fpga-faq.com/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm

Apply FPGA power
Wait 2ms
Set PROG_B to L
Wait 5us
Wait for INIT_L and DONE to be both L
Set PROB_B to H
Wait for INIT_L to transition to H
Wait 5us

Loop
Set CCLK to L
Set DIN to appropriate bit
SET CCLK to H
If DONE is H, break from loop
If INIT_L is L, break from loopendloop
Endloop

The problem occurs within the loop above. When DIN bits are correctly
injected (what I believe is correct), the DONE transitions to H before
the data is complete. This DONE high occurs at nibble 805842; whereas
the data size is 805873 nibbles (31 nibble difference). Furthermore,
if I send the data bit swapped (incorrect), the INIT_L drops low at
the same nibble 805842. If I feed the data in completely backwards, I
make it completely through the loop, never see an INIT_L to L signal,
but never see a DONE H either.

Two notes: First, I would expect the FPGA would flag a CRC or framing
error long before nibble 805842 when the data is deliberately
malformed. Second, it seems that the Xilinx ISE prom image generated
from iMPACT is too large (by 31 nibbles, or 124 bits). Also note that
the trailing bit data is NOT 'ff', as was specified in iMPACT.

// first 3 lines of nibble data generated as "hex no-swap"
const UNS_8 promData[] =
"ffffffffaa995566300080010000000730016001"
"000000643001200140003fe53001c00111428093"
"3000c00100000000300080010000000930002001"
..
..
..
// last 3 lines of nibble data generated as "hex no-swap".
"200000002000000030008001000000053000a001"
"000000003000000100005f57300080010000000d"
"200000002000000020000000200000000";


Any suggestions??

-W

From: DJ Delorie on 7 Sep 2009 19:45

Just to be sure - you're generating the headerless bitfile, not the
one with the header? I've got a board that does what you're doing,
and I have to generate the headerless bitfile for it to work properly.
From: Curt Johnson on 8 Sep 2009 10:54
wdeninger wrote:
> Hello,
>
<snip>
> Two notes: First, I would expect the FPGA would flag a CRC or framing
> error long before nibble 805842 when the data is deliberately
> malformed. Second, it seems that the Xilinx ISE prom image generated
> from iMPACT is too large (by 31 nibbles, or 124 bits). Also note that
> the trailing bit data is NOT 'ff', as was specified in iMPACT.
>
<snip>

The flow chart in the data sheet indicates that the CRC is checked after
the configuration data frames are loaded, not on a frame by frame basis.

The extra bits are part of the startup sequence. The DONE timing can be
changed with BitGen options, but basically, if you have DONE, and you
have shifted all of the bits, then you are good to go. Don't just stop
when you see DONE high, or you won't startup correctly.

Curt

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