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From: Seeker on 24 Mar 2010 01:54
On Mar 23, 6:02 pm, Gabor <ga...(a)alacron.com> wrote:
> On Mar 23, 6:19 am, Magne Munkejord <magnem...(a)yahoo.no> wrote:
>
>
>
>
>
> > Seeker wrote:
> > > On Mar 23, 2:07 pm, Magne Munkejord <magnem...(a)yahoo.no> wrote:
> > >> Hi,
>
> > >> Each address designates a 64 bit word in memory.
> > >> Are you sure about the FIFO's width? As far as I remember this was 128
> > >> bits for read and write data. The command FIFOs width is 36.
>
> > >> The DDR2 controller transmits 64 bits at rising and 64 bits at falling
> > >> edge of the clock, 128 bits per clock cycle.
>
> > >> A burst size of 8 means 8x64 bits words burst length which is 4x128 bits
> > >> words in your data FIFOs (read or write) per read/write command.
>
> > >> HTH,
>
> > >> Magne
>
> > > Thanks for the reply,
> > > You are right, the data FIFO is 128 bits wide.
> > > In case of a burst length of 4, every write command would have 2x128
> > > bits write (4x64 bits). If each address designates a 64 bit word in
> > > memory (which is what I thought), the addresses should be generated
> > > with an offset of 4 (since there are 4 64 bit words, each 64 bits
> > > corresponds to a location in memory), the addresses should progress
> > > like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation
> > > generated from MIG progresses the addresses with an offset of 8? Is it
> > > just to show writing and reading of the memory?
>
> > > Seeker...
>
> > Could be, but I remember that a burst length of 8 is also an option in
> > the MIG so maybe they made the testbench so that it would work for both
> > options (4 and 8 burst length) or maybe the testbench is confused which
> > option is set?
> > (by "offset of 8" I assume you mean increments of 8.)
>
> > Magne
>
> Maybe the testbench writer was just lazy and an offset of 8
> would "work" for either case because you never overwrite
> any data even though in the burst of 4 case you skip over
> half the available memory?
>
> - Gabor- Hide quoted text -
>
> - Show quoted text -

@Magne
I think you are right. I ran a simulation with the burst length of 8
and the address generation was following the same pattern.
Thanks everyone for your replies.


Seeker..
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