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From: Seeker on 22 Mar 2010 09:46
Hi,
I am using MIG 3.3 for generating memory interface for Micron
MT4HFT3264HY-53 memory part. The user_design and example_design
simulations work fine. I just need one clarification. The addresses
generated by the stimulus for the user interface (app_af_addr,
app_af_cmd, app_af_wren, app_wdf_data, app_wdf_wren etc) are at an
offset of 8 (design generated for sequential reads/writes with a burst
length of 4 for a single ended clock). I need to understand the
relationship of this address offset, is it related to the memory part
MT4HFT3264HY-53 ( 32M x 64) or is it related to the user address/data
FIFOs which are in 512x36 configuration.
anyone please?

Thanks

Seeker...
From: Magne Munkejord on 23 Mar 2010 05:07
Hi,

Each address designates a 64 bit word in memory.
Are you sure about the FIFO's width? As far as I remember this was 128
bits for read and write data. The command FIFOs width is 36.

The DDR2 controller transmits 64 bits at rising and 64 bits at falling
edge of the clock, 128 bits per clock cycle.

A burst size of 8 means 8x64 bits words burst length which is 4x128 bits
words in your data FIFOs (read or write) per read/write command.

HTH,

Magne
From: Seeker on 23 Mar 2010 06:01
On Mar 23, 2:07 pm, Magne Munkejord <magnem...(a)yahoo.no> wrote:
> Hi,
>
> Each address designates a 64 bit word in memory.
> Are you sure about the FIFO's width? As far as I remember this was 128
> bits for read and write data. The command FIFOs width is 36.
>
> The DDR2 controller transmits 64 bits at rising and 64 bits at falling
> edge of the clock, 128 bits per clock cycle.
>
> A burst size of 8 means 8x64 bits words burst length which is 4x128 bits
> words in your data FIFOs (read or write) per read/write command.
>
> HTH,
>
> Magne

Thanks for the reply,
You are right, the data FIFO is 128 bits wide.
In case of a burst length of 4, every write command would have 2x128
bits write (4x64 bits). If each address designates a 64 bit word in
memory (which is what I thought), the addresses should be generated
with an offset of 4 (since there are 4 64 bit words, each 64 bits
corresponds to a location in memory), the addresses should progress
like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation
generated from MIG progresses the addresses with an offset of 8? Is it
just to show writing and reading of the memory?

Seeker...
From: Magne Munkejord on 23 Mar 2010 06:19
Seeker wrote:
> On Mar 23, 2:07 pm, Magne Munkejord <magnem...(a)yahoo.no> wrote:
>> Hi,
>>
>> Each address designates a 64 bit word in memory.
>> Are you sure about the FIFO's width? As far as I remember this was 128
>> bits for read and write data. The command FIFOs width is 36.
>>
>> The DDR2 controller transmits 64 bits at rising and 64 bits at falling
>> edge of the clock, 128 bits per clock cycle.
>>
>> A burst size of 8 means 8x64 bits words burst length which is 4x128 bits
>> words in your data FIFOs (read or write) per read/write command.
>>
>> HTH,
>>
>> Magne
>
> Thanks for the reply,
> You are right, the data FIFO is 128 bits wide.
> In case of a burst length of 4, every write command would have 2x128
> bits write (4x64 bits). If each address designates a 64 bit word in
> memory (which is what I thought), the addresses should be generated
> with an offset of 4 (since there are 4 64 bit words, each 64 bits
> corresponds to a location in memory), the addresses should progress
> like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation
> generated from MIG progresses the addresses with an offset of 8? Is it
> just to show writing and reading of the memory?
>
> Seeker...

Could be, but I remember that a burst length of 8 is also an option in
the MIG so maybe they made the testbench so that it would work for both
options (4 and 8 burst length) or maybe the testbench is confused which
option is set?
(by "offset of 8" I assume you mean increments of 8.)

Magne
From: Gabor on 23 Mar 2010 09:02
On Mar 23, 6:19 am, Magne Munkejord <magnem...(a)yahoo.no> wrote:
> Seeker wrote:
> > On Mar 23, 2:07 pm, Magne Munkejord <magnem...(a)yahoo.no> wrote:
> >> Hi,
>
> >> Each address designates a 64 bit word in memory.
> >> Are you sure about the FIFO's width? As far as I remember this was 128
> >> bits for read and write data. The command FIFOs width is 36.
>
> >> The DDR2 controller transmits 64 bits at rising and 64 bits at falling
> >> edge of the clock, 128 bits per clock cycle.
>
> >> A burst size of 8 means 8x64 bits words burst length which is 4x128 bits
> >> words in your data FIFOs (read or write) per read/write command.
>
> >> HTH,
>
> >> Magne
>
> > Thanks for the reply,
> > You are right, the data FIFO is 128 bits wide.
> > In case of a burst length of 4, every write command would have 2x128
> > bits write (4x64 bits). If each address designates a 64 bit word in
> > memory (which is what I thought), the addresses should be generated
> > with an offset of 4 (since there are 4 64 bit words, each 64 bits
> > corresponds to a location in memory), the addresses should progress
> > like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation
> > generated from MIG progresses the addresses with an offset of 8? Is it
> > just to show writing and reading of the memory?
>
> > Seeker...
>
> Could be, but I remember that a burst length of 8 is also an option in
> the MIG so maybe they made the testbench so that it would work for both
> options (4 and 8 burst length) or maybe the testbench is confused which
> option is set?
> (by "offset of 8" I assume you mean increments of 8.)
>
> Magne

Maybe the testbench writer was just lazy and an offset of 8
would "work" for either case because you never overwrite
any data even though in the burst of 4 case you skip over
half the available memory?

- Gabor
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