Prev: Quartus Web Edition on Linux - no simulation?
Next: Connecting ADC chip to sparta 3 a dsp
From: Uwe Bonnes on 1 Feb 2010 05:38
Hello,

is there a way to constrain minimum hold time requirements with ISE?

I am trying to write to an FT2232H in synchronous FIFO mode. The FT2232H
supplies a 60 MHz clock and specifies 11 ns setup and 0 ns hold. As the
FT2232H supplied clock can stop, using a DCM to retime the clock will at
least require the DCM to stabilize each time and so to wait when the
transmission is initiated.

So only with the FT2232H on a global clock, all outputs using the PAD
registers and with a XC200A and LVCMOS25/12mA/Fast slew drive TICKOF is 5.24
ns and timing can be met (16.666 -5.24 = 11.42 > 11).

However this eats up simultaneous switching margins, and more my test board
uses 3.3V and the clock is on a LHCLK, not reaching all outputs.

Another way would be to clock out data on the negative edge with input delay
on the clock and a slow drive. If I could constrain half a clock period hold
time, the 0 ns hold requirement of the FT2232h could be met.

Is there a way to do so?

Any other ideas?

Thanks

--
Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: whygee on 1 Feb 2010 05:44
Uwe Bonnes wrote:
> Is there a way to do so?
> Any other ideas?
use a faster clock ?

> Thanks
hope this helps ;-)
yg

--
http://ygdes.com / http://yasep.org
From: rickman on 2 Feb 2010 18:49
On Feb 1, 5:38 am, Uwe Bonnes <b...(a)elektron.ikp.physik.tu-
darmstadt.de> wrote:
> Hello,
>
> is there a way to constrain minimum hold time requirements with ISE?
>
> I am trying to write to an FT2232H in synchronous FIFO mode. The FT2232H
> supplies a 60 MHz clock and specifies 11 ns setup and 0 ns hold. As the
> FT2232H supplied clock can stop, using a DCM to retime the clock will at
> least require the DCM to stabilize each time and so to wait when the
> transmission is initiated.
>
> So only with the FT2232H on a global clock, all outputs using the PAD
> registers and with a XC200A and LVCMOS25/12mA/Fast slew drive TICKOF is 5..24
> ns and timing can be met (16.666 -5.24 = 11.42 > 11).
>
> However this eats up simultaneous switching margins, and more my test board
> uses 3.3V and the clock is on a LHCLK, not reaching all outputs.
>
> Another way would be to clock out data on the negative edge with input delay
> on the clock and a slow drive. If I could constrain half a clock period hold
> time, the 0 ns hold requirement of the FT2232h could be met.
>
> Is there a way to do so?
>
> Any other ideas?

I'm not clear about your problem exactly. It looks like your system
meets the setup time of the FT2232H chip. The hold time requirement
is 0, so that is met for sure unless you have clock routing problems.
If your clock is on the wrong input, there is not much you can do
about that. I am pretty sure you will not find a real way to meet a
half clock time hold and not blow the setup time. In fact, I don't
really see where you are headed with this.

BTW, where did you get the 5.24 ns value? My concern is that the
calculation of this time is a bit messy requiring you go add more than
one offset to a base value as determined by the I/O modes. Did you do
all of that?

Rick
From: Brian Davis on 2 Feb 2010 21:15
Uwe Bonnes wrote:
>
> Any other ideas?
>
If the FPGA pin driving the FT2232H WR# pin is within your LHCLK
domain,
how about making WR# the only FAST output pin, and then enable writes
on every other clock cycle.

This would cut your transfer rate to 30 Mbytes/sec max into the
fifo,
but give you two clocks of setup for the data lines.

( I've never used the FT2232H; the data sheet mentions a max transfer
rate >= 25 MB/s in synchronous mode, and it looks like you have to
monitor the TXE# line to stall writes if the FT2232H isn't ready. )

>
> Another way would be to clock out data on the negative edge with input delay
> on the clock and a slow drive. If I could constrain half a clock period hold
> time, the 0 ns hold requirement of the FT2232h could be met.
>
> Is there a way to do so?

I would not recommend this scheme.

With a 16.67 ns clock period, starting at the falling edge you'd need
to
delay the data outputs at least 8.33 ns ( to meet the hold time ) but
no
more than 8.33 + ( 16.67 - 11 )= 14 ns to meet the next clock's setup
time.
So you'd need to hold your I/O's switching time to be within a 5.67 ns
absolute window, whilst using slow I/O's with no DLL in the clock
tree.

Brian
From: Uwe Bonnes on 4 Feb 2010 05:08
rickman <gnuarm(a)gmail.com> wrote:
>...
> I'm not clear about your problem exactly. It looks like your system
> meets the setup time of the FT2232H chip. The hold time requirement
> is 0, so that is met for sure unless you have clock routing problems.
> If your clock is on the wrong input, there is not much you can do
> about that. I am pretty sure you will not find a real way to meet a
> half clock time hold and not blow the setup time. In fact, I don't
> really see where you are headed with this.

While the idea of half a clock hold time at the output was not my brightest,
the question of specifying hold time requirements in general remains.

> BTW, where did you get the 5.24 ns value?

It's the value form the ds529 datasheet.

> My concern is that the
> calculation of this time is a bit messy requiring you go add more than
> one offset to a base value as determined by the I/O modes. Did you do
> all of that?

The post layout timing uses this value too (and some adders for IO voltage,
rate and drive)

Bye
--
Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 |  Next  |  Last
Pages: 1 2 3
Prev: Quartus Web Edition on Linux - no simulation?
Next: Connecting ADC chip to sparta 3 a dsp