From: Pete Fraser on
I am working on a project where I need to
implement 6-th order Butterworth low-pass
filters in an FPGA. In some the bandwidth is
low relative to the input data rate, whereas
others have higher bandwidth. I can use ScopeIIR
or Matlab to give me a good idea of coefficient
accuracy for any given ratio of bandwidth to
input sample rate.

However, I'm not sure what data-path accuracy
I need (for 20-bit input / output accuracy).
Is there a rule-of-thumb I can use, or do I just
have to simulate the filter with real data and
see what gives me low enough noise?

I was planning on using biquads, but I'm not sure
whether I'm better off with DF1 or DF2 sections.

Thoughts?

Thanks

Pete



From: Vladimir Vassilevsky on


Pete Fraser wrote:

> I am working on a project where I need to
> implement 6-th order Butterworth low-pass
> filters in an FPGA. In some the bandwidth is
> low relative to the input data rate, whereas
> others have higher bandwidth. I can use ScopeIIR
> or Matlab to give me a good idea of coefficient
> accuracy for any given ratio of bandwidth to
> input sample rate.
>
> However, I'm not sure what data-path accuracy
> I need (for 20-bit input / output accuracy).
> Is there a rule-of-thumb I can use, or do I just
> have to simulate the filter with real data and
> see what gives me low enough noise?
>
> I was planning on using biquads, but I'm not sure
> whether I'm better off with DF1 or DF2 sections.

If the filter cutoff frequency is much lower then samplerate, then loss
of precision in the direct implementation of the biquad section could be
very roughly estimated as ~ Q (Fc/Fs)^2.

Let's say Fc = 100 kHz, Fs = 100 Hz, Q = 1. Loss of precision ~ 1e6 ~ 20
bits. That is, if your filter is implemented with 32 bit data path, the
result will be accurate only to 12 bits.

There are, of course, methods to get more accurate estimates and to
improve precision, however this is a different and rather long story.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com









From: Steve Pope on
Pete Fraser <pfraser(a)covad.net> wrote:

>I am working on a project where I need to
>implement 6-th order Butterworth low-pass
>filters in an FPGA. In some the bandwidth is
>low relative to the input data rate, whereas
>others have higher bandwidth. I can use ScopeIIR
>or Matlab to give me a good idea of coefficient
>accuracy for any given ratio of bandwidth to
>input sample rate.
>
>However, I'm not sure what data-path accuracy
>I need (for 20-bit input / output accuracy).
>Is there a rule-of-thumb I can use, or do I just
>have to simulate the filter with real data and
>see what gives me low enough noise?

You should simulate the fixed-point filter. When simulating,
you do not necessarily have to stimulate it with realistic data. I
often will stimulate the design being tested with bandlimited noise, and
measure the RMS error of output (relative to the same design, but in full
floating-point). Plotting the RMS error (in dBc) vs. RMS input level
gives you a very good idea of the dynamic range of the fixed point
design.

>I was planning on using biquads, but I'm not sure
>whether I'm better off with DF1 or DF2 sections.

You can do this, or you can use a lattice topology
(called "ARMA" in matlab/fdatool), which is the most
well-behaved topology.

Steve
From: robert bristow-johnson on
On Jul 29, 3:23 pm, "Pete Fraser" <pfra...(a)covad.net> wrote:
> I am working on a project where I need to
> implement 6-th order Butterworth low-pass
> filters in an FPGA. In some the bandwidth is
> low relative to the input data rate, whereas
> others have higher bandwidth. I can use ScopeIIR
> or Matlab to give me a good idea of coefficient
> accuracy for any given ratio of bandwidth to
> input sample rate.
>
> However, I'm not sure what data-path accuracy
> I need (for 20-bit input / output accuracy).
> Is there a rule-of-thumb I can use, or do I just
> have to simulate the filter with real data and
> see what gives me low enough noise?
>
> I was planning on using biquads, but I'm not sure
> whether I'm better off with DF1 or DF2 sections.
>
> Thoughts?

i think you'll do better with DF1 sections (it will cost you two more
storage states, you'll have 8 instead of 6) and, for each section, an
accumulator that is wide enough to have no error given the word widths
of the signal (you said 20 bits) and the coefficients (that might
depend on the range of coefficients).

using 1st-order error shaping, a.k.a. "fraction saving" might gain you
something, and you can accomplish this for free if you leave in your
accumulator (as an initial value) the long-word output from the
previous sample. you will need to compensate this by subtracting 1
from "a1", the first feedback coefficient. then, for rounding to the
next section, all you need to do is truncate the low-order bits of the
word going to the next section, no rounding necessary (that gets fixed
with the fraction saving). that means, for

H(z) = N(z)/D(z)

where

D(z) = 1 + a1*z^(-1) + a2*z^(-2)

= 1 + (a1+1)*z^(-1) - z^(-1) + a2*z^(-2)

the term z^(-1) would be the double wide output from the previous
sample, y[n-1].


if your biquads remain resonant (meaning complex conjugate poles) and
if the resonant frequency is going to be very low and if the resonance
will be high (that is the poles are close to z=1), then consider
reworking the denominator of the biquad transfer function as:


D(z) = 1 + a1*z^(-1) + a2*z^(-2)

= 1 + (a1+2)*z^(-1) - 2*z^(-1) + (a2-1)*z^(-2) + z^(-2)


for the terms 2*z^(-1) and z^(-2), you would use the double-wide
previous states of y[n-1] and y[n-2].

just a recommendation i might make to make your life easier in the
universe of fixed-point arithmetic.

> Thanks

FWIW.

r b-j

From: Manny on
On Jul 29, 8:47 pm, spop...(a)speedymail.org (Steve Pope) wrote:
> Pete Fraser <pfra...(a)covad.net> wrote:
> >I am working on a project where I need to
> >implement 6-th order Butterworth low-pass
> >filters in an FPGA. In some the bandwidth is
> >low relative to the input data rate, whereas
> >others have higher bandwidth. I can use ScopeIIR
> >or Matlab to give me a good idea of coefficient
> >accuracy for any given ratio of bandwidth to
> >input sample rate.
>
> >However, I'm not sure what data-path accuracy
> >I need (for 20-bit input / output accuracy).
> >Is there a rule-of-thumb I can use, or do I just
> >have to simulate the filter with real data and
> >see what gives me low enough noise?
>
> You should simulate the fixed-point filter.  When simulating,
> you do not necessarily have to stimulate it with realistic data.  I
> often will stimulate the design being tested with bandlimited noise, and
> measure the RMS error of output (relative to the same design, but in full
> floating-point).  Plotting the RMS error (in dBc) vs. RMS input level
> gives you a very good idea of the dynamic range of the fixed point
> design.
>
> >I was planning on using biquads, but I'm not sure
> >whether I'm better off with DF1 or DF2 sections.
>
> You can do this, or you can use a lattice topology
> (called "ARMA" in matlab/fdatool), which is the most
> well-behaved topology.
>
> Steve

I recently did just that and concurs with everything Steve said. Most
important figure you need to keep track of is your I/O RMS with the
various quantizations and casts you'd have applied. The places where
casting occurs is of particular importance here and is structure-
related. If your realization is sequential it'd be even harder to sort
out. My final filter was DF2 with a shared biquad core and a memory
trace for states and biquad inputs and outputs. The best performance
for casting you get from convergent. Keep simulating various scenarios
and look at your RMS and play with your structure, quantization, and
castings until you land something satisfactory. Looking at my core's
generics, here are what worked quite well for me:
- core: rolled IIR DF2 SOS
- sample word width: 16
- internal state width: 25
- internal fract width: 15
- coeff word width: 17
- coeff fract width: 15
- output scaling: YES

Regards,
-Momo