Dealing with SPI ADC timings
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From: ElVale on 20 Oct 2009 11:55 I'd like to implement an SPI master to read an AD7924 ADC. The thing is that there are some setup and hold time I have to respect, ie CS'to SCLK setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns to 50 ns. What's the best way to implement these delays?
From: ElVale on 20 Oct 2009 12:12 >I'd like to implement an SPI master to read an AD7924 ADC. The thing is >that there are some setup and hold time I have to respect, ie CS'to SCLK >setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns >to 50 ns. > >What's the best way to implement these delays? > > > I mean implementing them in VHDL. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Marc Jet on 20 Oct 2009 12:54 > What's the best way to implement these delays? You can easily implement them with a state machine that is clocked considerably faster than the SPI bit rate.
From: Arlet on 20 Oct 2009 13:36
On Tue, 20 Oct 2009 10:55:57 -0500, ElVale wrote: > I'd like to implement an SPI master to read an AD7924 ADC. The thing is > that there are some setup and hold time I have to respect, ie CS'to SCLK > setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns > to 50 ns. > > What's the best way to implement these delays? If the FPGA is too fast, add some dummy states to your state machine where you don't change the outputs. |