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From: Speed on 8 Apr 2010 23:57
Dear All,
We are planning to design a board with four FPGAs to emulate X86
CPU. The FPGA’s JTAG ports are serially chained together. My problem
is that whether the Xilinx’s ChipScope can support debugging multiple
FPGAs via a single JTAG chain at the same time? So we can set
different trigger conditions to different FPGA chips at the same time
and watch the sampled data from ChipScope.


Thanks in advance,
Speed.
From: HT-Lab on 9 Apr 2010 03:26
I am not sure about ChipScope (Pro) but Dialite from Temento can do this and can
also handle mixed vendors.

http://www.temento.com/index.php?rubrique=15

Do you really need 4 FPGAs?

Hans
www.ht-lab.com



"Speed" <speedboy1211(a)gmail.com> wrote in message
news:faa559c2-2ef8-440c-b9bc-3ccd212528fd(a)u31g2000yqb.googlegroups.com...
Dear All,
We are planning to design a board with four FPGAs to emulate X86
CPU. The FPGA�s JTAG ports are serially chained together. My problem
is that whether the Xilinx�s ChipScope can support debugging multiple
FPGAs via a single JTAG chain at the same time? So we can set
different trigger conditions to different FPGA chips at the same time
and watch the sampled data from ChipScope.


Thanks in advance,
Speed.


From: Ed McGettigan on 9 Apr 2010 09:55
On Apr 8, 11:57 pm, Speed <speedboy1...(a)gmail.com> wrote:
> Dear All,
>   We are planning to design a board with four FPGAs to emulate X86
> CPU. The FPGA’s JTAG ports are serially chained together. My problem
> is that whether the Xilinx’s ChipScope can support debugging multiple
> FPGAs via a single JTAG chain at the same time? So we can set
> different trigger conditions to different FPGA chips at the same time
> and watch the sampled data from ChipScope.
>
> Thanks in advance,
> Speed.

Yes, ChipScope can handle debugging in multiple FPGAs in the same
chain. Each of the ILA cores will be independent of each other.

Ed McGettigan
--
Xilinx Inc.
From: Speed on 11 Apr 2010 23:03
On Apr 9, 9:55 pm, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote:
> On Apr 8, 11:57 pm, Speed <speedboy1...(a)gmail.com> wrote:
>
> > Dear All,
> >   We are planning to design a board with four FPGAs to emulate X86
> > CPU. The FPGA’s JTAG ports are serially chained together. My problem
> > is that whether the Xilinx’s ChipScope can support debugging multiple
> > FPGAs via a single JTAG chain at the same time? So we can set
> > different trigger conditions to different FPGA chips at the same time
> > and watch the sampled data from ChipScope.
>
> > Thanks in advance,
> > Speed.
>
> Yes, ChipScope can handle debugging in multiple FPGAs in the same
> chain.  Each of the ILA cores will be independent of each other.
>
> Ed McGettigan
> --
> Xilinx Inc.

Dear Ed

Thanks for your replay

From: Nial Stewart on 12 Apr 2010 05:13
> "Speed" <speedboy1211(a)gmail.com> wrote in message
> news:faa559c2-2ef8-440c-b9bc-3ccd212528fd(a)u31g2000yqb.googlegroups.com...
> Dear All,
> We are planning to design a board with four FPGAs to emulate X86
> CPU. The FPGA�s JTAG ports are serially chained together. My problem
> is that whether the Xilinx�s ChipScope can support debugging multiple
> FPGAs via a single JTAG chain at the same time? So we can set
> different trigger conditions to different FPGA chips at the same time
> and watch the sampled data from ChipScope.


Speed,

I hope you'll forgive the 'advert' but depending on what you're trying to
look at in each of the FPGA's you might find my 1 Pin Interface useful...

http://www.1pin-interface.com/

There are five IO ports, the active one can be set on the fly so you could
use one module to access your 4 FPGAs. This gives high level register access
to the devices using just one unused user IO per device.

It might be easier to get up and running than 4 instances of chipscope.



Nial



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