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From: Griffin on 8 Apr 2010 09:51
Hello,

I'm a graduate student and I have a project on the ML402 (Virtex-4)
board under EDK 11.2, and I am unable to download a specific ELF I
have created to the board. Other software applications (both EDK
generated and programmed by myself) can be successfully downloaded and
run as part of this EDK project, but not the one I am currently work
on.

The following is the output I receive:
====
XMD% dow udp_temac_test/executable.elf
System Reset .... DONE
Downloading Program -- udp_temac_test/executable.elf
section, .vectors.reset: 0x00000000-0x00000003
section, .vectors.sw_exception: 0x00000008-0x0000000b
section, .vectors.interrupt: 0x00000010-0x00000013
section, .vectors.hw_exception: 0x00000020-0x00000023
section, .text: 0x00000050-0x00012c3b
section, .init: 0x00012c3c-0c00012c63
section.fini: 0x00012c64-0x00012c83
ERROR: Failed to download ELF file.

I-Side Memory Access Check Failed
Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side
Interface

====

Had anyone had this issue before? Anyone have any idea what might be
causing it / how to solve it?

Thanks in advance,

Sean.
From: Griffin on 8 Apr 2010 11:40
I have included my .mhs file:


#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.2 Build
EDK_LS2.6
# Mon Mar 8 17:09:28 2010
# Target Board: Xilinx Virtex 4 ML402 Evaluation Platform Rev 1
# Family: virtex4
# Device: xc4vsx35
# Package: ff668
# Speed Grade: -10
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 100.0
# Debug Interface: On-Chip HW Debug Module
#
##############################################################################
PARAMETER VERSION = 2.1.0


PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR
= O
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR =
O
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin,
DIR = O
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =
fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin,
DIR = O, VEC = [12:0]
PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR =
IO, VEC = [31:0]
PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR =
O, VEC = [3:0]
PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR
= IO, VEC = [3:0]
PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO_pin, DIR
= IO, VEC = [0:3]
PORT fpga_0_LEDs_Positions_GPIO_IO_pin =
fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX_pin, DIR = I
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX_pin, DIR = O
PORT fpga_0_SRAM_Mem_A_pin =
fpga_0_SRAM_Mem_A_pin_vslice_7_29_concat, DIR = O, VEC = [7:29]
PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC
= [0:3]
PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR =
O
PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC =
[0:31]
PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = clk_100_0000MHzDCM0, DIR = O
PORT fpga_0_Soft_TEMAC_TemacPhy_RST_n_pin =
fpga_0_Soft_TEMAC_TemacPhy_RST_n_pin, DIR = O
PORT fpga_0_Soft_TEMAC_MII_TX_CLK_0_pin =
fpga_0_Soft_TEMAC_MII_TX_CLK_0_pin, DIR = I
PORT fpga_0_Soft_TEMAC_GMII_TXD_0_pin =
fpga_0_Soft_TEMAC_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
PORT fpga_0_Soft_TEMAC_GMII_TX_EN_0_pin =
fpga_0_Soft_TEMAC_GMII_TX_EN_0_pin, DIR = O
PORT fpga_0_Soft_TEMAC_GMII_TX_ER_0_pin =
fpga_0_Soft_TEMAC_GMII_TX_ER_0_pin, DIR = O
PORT fpga_0_Soft_TEMAC_GMII_TX_CLK_0_pin =
fpga_0_Soft_TEMAC_GMII_TX_CLK_0_pin, DIR = O
PORT fpga_0_Soft_TEMAC_GMII_RXD_0_pin =
fpga_0_Soft_TEMAC_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
PORT fpga_0_Soft_TEMAC_GMII_RX_DV_0_pin =
fpga_0_Soft_TEMAC_GMII_RX_DV_0_pin, DIR = I
PORT fpga_0_Soft_TEMAC_GMII_RX_ER_0_pin =
fpga_0_Soft_TEMAC_GMII_RX_ER_0_pin, DIR = I
PORT fpga_0_Soft_TEMAC_GMII_RX_CLK_0_pin =
fpga_0_Soft_TEMAC_GMII_RX_CLK_0_pin, DIR = I
PORT fpga_0_Soft_TEMAC_MDC_0_pin = fpga_0_Soft_TEMAC_MDC_0_pin, DIR =
O
PORT fpga_0_Soft_TEMAC_MDIO_0_pin = fpga_0_Soft_TEMAC_MDIO_0_pin, DIR
= IO
PORT fpga_0_Soft_TEMAC_PHY_INTR_pin = fpga_0_Soft_TEMAC_PHY_INTR_pin,
DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW,
INTERRUPT_PRIORITY = MEDIUM
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =
fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =
fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =
fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK,
CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST,
RST_POLARITY = 0
PORT event_getter_0_pixels_in_pin = event_getter_0_pixels_in, DIR =
I, VEC = [0:6]
PORT event_getter_0_pixels_out_pin = event_getter_0_pixels_out, DIR =
O, VEC = [0:6]
PORT sv_timer_0_timer_expired_watch_pin =
sv_timer_0_timer_expired_watch, DIR = O
PORT sv_timer_0_hard_reset_pin = sv_timer_0_hard_reset, DIR = I
PORT si_timer_0_hard_reset_pin = si_timer_0_hard_reset, DIR = I
PORT si_timer_0_timer_expired_watch_pin =
si_timer_0_timer_expired_watch, DIR = O

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Intr = Soft_TEMAC_fifo_IP2INTC_Irpt&si_timer_irc
PORT Irq = microblaze_0_Interrupt
END

BEGIN si_timer
PARAMETER INSTANCE = si_timer_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xca020000
PARAMETER C_HIGHADDR = 0xca02ffff
BUS_INTERFACE SPLB = mb_plb
PORT IP2INTC_Irpt = si_timer_irc
PORT hard_reset = si_timer_0_hard_reset
PORT timer_expired_watch = si_timer_0_timer_expired_watch
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 2.00.a
PORT Slowest_sync_clk = clk_100_0000MHzDCM0
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_FAMILY = virtex4
PARAMETER C_INTERCONNECT = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0x88300000
PARAMETER C_ICACHE_HIGHADDR = 0x883fffff
PARAMETER C_CACHE_BYTE_SIZE = 65536
PARAMETER C_ICACHE_ALWAYS_USED = 1
PARAMETER C_DCACHE_BASEADDR = 0x88300000
PARAMETER C_DCACHE_HIGHADDR = 0x883fffff
PARAMETER C_DCACHE_BYTE_SIZE = 65536
PARAMETER C_DCACHE_ALWAYS_USED = 1
PARAMETER HW_VER = 7.20.b
PARAMETER C_USE_ICACHE = 1
PARAMETER C_USE_DCACHE = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DXCL = microblaze_0_DXCL
BUS_INTERFACE IXCL = microblaze_0_IXCL
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_Interrupt
END

BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER HW_VER = 1.00.f
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER C_FAMILY = virtex4
PARAMETER HW_VER = 1.04.a
PORT PLB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER C_FAMILY = virtex4
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END

# PORT pixels_in = event_getter_0_pixels_in
# PORT pixels_out = event_getter_0_pixels_out
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = clk_100_0000MHzDCM0
PORT SYS_Rst = sys_bus_reset
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_PHASE = 90
PARAMETER C_CLKOUT0_GROUP = DCM0
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_FREQ = 125000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = NONE
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT3_FREQ = 200000000
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = NONE
PARAMETER C_CLKOUT3_BUF = TRUE
PARAMETER HW_VER = 3.01.a
PORT CLKIN = dcm_clk_s
PORT CLKOUT0 = clk_100_0000MHz90DCM0
PORT CLKOUT1 = clk_100_0000MHzDCM0
PORT CLKOUT2 = clk_125_0000MHz
PORT CLKOUT3 = clk_200_0000MHz
PORT RST = net_gnd
PORT LOCKED = Dcm_all_locked
END

BEGIN xps_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER C_MEM_WIDTH = 16
PARAMETER C_FAMILY = virtex4
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x83600000
PARAMETER C_HIGHADDR = 0x8360ffff
BUS_INTERFACE SPLB = mb_plb
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
END

BEGIN xps_ll_fifo
PARAMETER INSTANCE = Soft_TEMAC_fifo
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x81a00000
PARAMETER C_HIGHADDR = 0x81a0ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE LLINK = Soft_TEMAC_llink0
PORT IP2INTC_Irpt = Soft_TEMAC_fifo_IP2INTC_Irpt
END

BEGIN xps_ll_temac
PARAMETER INSTANCE = Soft_TEMAC
PARAMETER C_NUM_IDELAYCTRL = 3
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y4-IDELAYCTRL_X2Y4-
IDELAYCTRL_X2Y5
PARAMETER C_FAMILY = virtex4
PARAMETER C_PHY_TYPE = 1
PARAMETER C_TEMAC1_ENABLED = 0
PARAMETER C_BUS2CORE_CLK_RATIO = 1
PARAMETER C_TEMAC_TYPE = 2
PARAMETER C_TEMAC0_PHYADDR = 0b00001
PARAMETER HW_VER = 2.02.a
PARAMETER C_BASEADDR = 0x81c00000
PARAMETER C_HIGHADDR = 0x81c0ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE LLINK0 = Soft_TEMAC_llink0
PORT TemacPhy_RST_n = fpga_0_Soft_TEMAC_TemacPhy_RST_n_pin
PORT GTX_CLK_0 = clk_125_0000MHz
PORT REFCLK = clk_200_0000MHz
PORT LlinkTemac0_CLK = clk_100_0000MHzDCM0
PORT MII_TX_CLK_0 = fpga_0_Soft_TEMAC_MII_TX_CLK_0_pin
PORT GMII_TXD_0 = fpga_0_Soft_TEMAC_GMII_TXD_0_pin
PORT GMII_TX_EN_0 = fpga_0_Soft_TEMAC_GMII_TX_EN_0_pin
PORT GMII_TX_ER_0 = fpga_0_Soft_TEMAC_GMII_TX_ER_0_pin
PORT GMII_TX_CLK_0 = fpga_0_Soft_TEMAC_GMII_TX_CLK_0_pin
PORT GMII_RXD_0 = fpga_0_Soft_TEMAC_GMII_RXD_0_pin
PORT GMII_RX_DV_0 = fpga_0_Soft_TEMAC_GMII_RX_DV_0_pin
PORT GMII_RX_ER_0 = fpga_0_Soft_TEMAC_GMII_RX_ER_0_pin
PORT GMII_RX_CLK_0 = fpga_0_Soft_TEMAC_GMII_RX_CLK_0_pin
PORT MDC_0 = fpga_0_Soft_TEMAC_MDC_0_pin
PORT MDIO_0 = fpga_0_Soft_TEMAC_MDIO_0_pin
END

BEGIN xps_mch_emc
PARAMETER INSTANCE = SRAM
PARAMETER C_FAMILY = virtex4
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CHANNELS = 2
PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
PARAMETER C_MEM0_WIDTH = 32
PARAMETER C_MAX_MEM_WIDTH = 32
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
PARAMETER C_SYNCH_MEM_0 = 1
PARAMETER C_TCEDV_PS_MEM_0 = 0
PARAMETER C_TAVDV_PS_MEM_0 = 0
PARAMETER C_THZCE_PS_MEM_0 = 0
PARAMETER C_TWC_PS_MEM_0 = 0
PARAMETER C_TWP_PS_MEM_0 = 0
PARAMETER C_TLZWE_PS_MEM_0 = 0
PARAMETER HW_VER = 3.00.a
PARAMETER C_MEM0_BASEADDR = 0x88300000
PARAMETER C_MEM0_HIGHADDR = 0x883fffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MCH0 = microblaze_0_IXCL
BUS_INTERFACE MCH1 = microblaze_0_DXCL
PORT RdClk = clk_100_0000MHzDCM0
PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_29_concat &
0b00
PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart
PARAMETER C_FAMILY = virtex4
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_RX_pin
PORT TX = fpga_0_RS232_Uart_TX_pin
END

BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_Positions
PARAMETER C_FAMILY = virtex4
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
END

BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_4Bit
PARAMETER C_FAMILY = virtex4
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO_pin
END

BEGIN xps_iic
PARAMETER INSTANCE = IIC_EEPROM
PARAMETER C_IIC_FREQ = 100000
PARAMETER C_TEN_BIT_ADR = 0
PARAMETER C_FAMILY = virtex4
PARAMETER HW_VER = 2.01.a
PARAMETER C_BASEADDR = 0x81600000
PARAMETER C_HIGHADDR = 0x8160ffff
BUS_INTERFACE SPLB = mb_plb
PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
END

BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM
PARAMETER C_FAMILY = virtex4
PARAMETER C_NUM_PORTS = 1
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X0Y5
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_MEM_PARTNO = HYB25D256160BT-7
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MEM_DM_WIDTH = 4
PARAMETER C_MEM_DQS_WIDTH = 4
PARAMETER C_PIM0_BASETYPE = 2
PARAMETER HW_VER = 5.02.a
PARAMETER C_MPMC_BASEADDR = 0x8c000000
PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
BUS_INTERFACE SPLB0 = mb_plb
PORT MPMC_Clk0 = clk_100_0000MHzDCM0
PORT MPMC_Clk90 = clk_100_0000MHz90DCM0
PORT MPMC_Clk_200MHz = clk_200_0000MHz
PORT MPMC_Rst = sys_periph_reset
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin
PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin
END

BEGIN event_getter
PARAMETER INSTANCE = event_getter_0
PARAMETER HW_VER = 1.03.a
PARAMETER C_BASEADDR = 0xcf400000
PARAMETER C_HIGHADDR = 0xcf40ffff
BUS_INTERFACE SPLB = mb_plb
PORT pixels_in = event_getter_0_pixels_in
PORT pixels_out = event_getter_0_pixels_out
END

BEGIN sv_timer
PARAMETER INSTANCE = sv_timer_0
PARAMETER HW_VER = 2.04.a
PARAMETER C_BASEADDR = 0xca000000
PARAMETER C_HIGHADDR = 0xca00ffff
BUS_INTERFACE SPLB = mb_plb
PORT timer_expired_watch = sv_timer_0_timer_expired_watch
PORT hard_reset = sv_timer_0_hard_reset
END





On Apr 8, 9:51 am, Griffin <captain.grif...(a)gmail.com> wrote:
> Hello,
>
> I'm a graduate student and I have a project on the ML402 (Virtex-4)
> board under EDK 11.2, and I am unable to download a specific ELF I
> have created to the board. Other software applications (both EDK
> generated and programmed by myself) can be successfully downloaded and
> run as part of this EDK project, but not the one I am currently work
> on.
>
> The following is the output I receive:
> ====
> XMD% dow udp_temac_test/executable.elf
> System Reset .... DONE
> Downloading Program -- udp_temac_test/executable.elf
> section, .vectors.reset: 0x00000000-0x00000003
> section, .vectors.sw_exception: 0x00000008-0x0000000b
> section, .vectors.interrupt: 0x00000010-0x00000013
> section, .vectors.hw_exception: 0x00000020-0x00000023
> section, .text: 0x00000050-0x00012c3b
> section, .init: 0x00012c3c-0c00012c63
> section.fini: 0x00012c64-0x00012c83
> ERROR: Failed to download ELF file.
>
> I-Side Memory Access Check Failed
> Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side
> Interface
>
> ====
>
> Had anyone had this issue before? Anyone have any idea what might be
> causing it / how to solve it?
>
> Thanks in advance,
>
> Sean.

From: Gabor on 8 Apr 2010 17:25
On Apr 8, 9:51 am, Griffin <captain.grif...(a)gmail.com> wrote:
> Hello,
>
> I'm a graduate student and I have a project on the ML402 (Virtex-4)
> board under EDK 11.2, and I am unable to download a specific ELF I
> have created to the board. Other software applications (both EDK
> generated and programmed by myself) can be successfully downloaded and
> run as part of this EDK project, but not the one I am currently work
> on.
>
> The following is the output I receive:
> ====
> XMD% dow udp_temac_test/executable.elf
> System Reset .... DONE
> Downloading Program -- udp_temac_test/executable.elf
> section, .vectors.reset: 0x00000000-0x00000003
> section, .vectors.sw_exception: 0x00000008-0x0000000b
> section, .vectors.interrupt: 0x00000010-0x00000013
> section, .vectors.hw_exception: 0x00000020-0x00000023
> section, .text: 0x00000050-0x00012c3b
> section, .init: 0x00012c3c-0c00012c63
> section.fini: 0x00012c64-0x00012c83
> ERROR: Failed to download ELF file.
>
> I-Side Memory Access Check Failed
> Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side
> Interface
>
> ====
>
> Had anyone had this issue before? Anyone have any idea what might be
> causing it / how to solve it?
>
> Thanks in advance,
>
> Sean.

Just a guess, but are you sure your .elf file isn't too big
to fit in memory? I see:

> Section, 0x00000050-0x00012c3b Not Accessible from Processor I-Side

and:

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

Which seems to imply that you have 64K of BRAM and a
somewhat larger .elf file. Are you trying to load
this into internal block RAM or do you have an external
SDRAM memory?

Regards,
Gabor
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