Design passes synthesis and routing but fails on FPGA
in [FPGA]
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From: Rob Gaddi on 9 Jun 2010 18:11 On 6/9/2010 9:45 AM, BrandonD wrote: > By being familiar with synthesis, I mean I'm a student and have had some > coursework with the design and synthesis, but projects ended there. To be > honest, they were more on the design aspect so I am familiar with the > synthesis process but not too experienced with it. > > I do not use any gated clocks and all of my sequential logic runs of the > same edge of the same 50 MHz clock except for the reset logic when the DCM > is stabilizing. > > I have not set any OFFSET IN/OUT constraints, do you know where I can get > more information about doing that? > > Thanks, > Brandon > >> On 6/9/2010 8:01 AM, BrandonD wrote: >>> Hi, >>> >>> I'm somewhat familiar with synthesis and Verilog but I am quite new to >>> running the designs on FPGAs. I have a complex design of a processor > that I >>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The > design >>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1 > but >>> it does not seem to run correctly when programmed on the FPGA. >>> >>> ISE says that all timing constraints have been met and the static > timing >>> report shows that it does too. What I am going to do now is look at the >>> post-par simulation and see if there's a problem. Is there anything > that >>> maybe is a common mistake that I should also look into? >>> >>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. > Any >>> suggestions will be appreciated. >>> >>> Thanks, >>> Brandon >>> >>> >>> >>> --------------------------------------- >>> Posted through http://www.FPGARelated.com >> >> Anything other than single clock synchronous logic isn't represented in >> your timing constraints; so anywhere that you're using a clock other >> than your derived 50 is worth another look. This includes any logic >> running off of a combinationally gated clock. You said you're used to >> synthesis but not FPGAs; if that means ASICs then one thing to be aware >> of is that clock nets are a lot more sacred in FPGAs. >> >> Unless you've specified your external OFFSET IN/OUT constraints properly >> (this is rare), then your constraints don't properly cover your >> relationships to external hardware. Worth another look. >> >> -- >> Rob Gaddi, Highland Technology >> Email address is currently out of order >> > > --------------------------------------- > Posted through http://www.FPGARelated.com I hope this is a stupid question but....it does simulate correctly, right? -- Rob Gaddi, Highland Technology Email address is currently out of order
From: BrandonD on 10 Jun 2010 02:47 It does simulate behaviorally correctly. I forgot to mention that part. You were right about the loop of the reset signal back to the DCM. I did exactly that. I've fixed that problem and it still appears to be working incorrectly. I am going to try post-par simulation to see how that looks. I will read up on the constraints as well. >On 6/9/2010 9:45 AM, BrandonD wrote: >> By being familiar with synthesis, I mean I'm a student and have had some >> coursework with the design and synthesis, but projects ended there. To be >> honest, they were more on the design aspect so I am familiar with the >> synthesis process but not too experienced with it. >> >> I do not use any gated clocks and all of my sequential logic runs of the >> same edge of the same 50 MHz clock except for the reset logic when the DCM >> is stabilizing. >> >> I have not set any OFFSET IN/OUT constraints, do you know where I can get >> more information about doing that? >> >> Thanks, >> Brandon >> >>> On 6/9/2010 8:01 AM, BrandonD wrote: >>>> Hi, >>>> >>>> I'm somewhat familiar with synthesis and Verilog but I am quite new to >>>> running the designs on FPGAs. I have a complex design of a processor >> that I >>>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The >> design >>>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1 >> but >>>> it does not seem to run correctly when programmed on the FPGA. >>>> >>>> ISE says that all timing constraints have been met and the static >> timing >>>> report shows that it does too. What I am going to do now is look at the >>>> post-par simulation and see if there's a problem. Is there anything >> that >>>> maybe is a common mistake that I should also look into? >>>> >>>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. >> Any >>>> suggestions will be appreciated. >>>> >>>> Thanks, >>>> Brandon >>>> >>>> >>>> >>>> --------------------------------------- >>>> Posted through http://www.FPGARelated.com >>> >>> Anything other than single clock synchronous logic isn't represented in >>> your timing constraints; so anywhere that you're using a clock other >>> than your derived 50 is worth another look. This includes any logic >>> running off of a combinationally gated clock. You said you're used to >>> synthesis but not FPGAs; if that means ASICs then one thing to be aware >>> of is that clock nets are a lot more sacred in FPGAs. >>> >>> Unless you've specified your external OFFSET IN/OUT constraints properly >>> (this is rare), then your constraints don't properly cover your >>> relationships to external hardware. Worth another look. >>> >>> -- >>> Rob Gaddi, Highland Technology >>> Email address is currently out of order >>> >> >> --------------------------------------- >> Posted through http://www.FPGARelated.com > >I hope this is a stupid question but....it does simulate correctly, right? > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order > --------------------------------------- Posted through http://www.FPGARelated.com
From: Matthieu Michon on 10 Jun 2010 03:26 On Wed, 9 Jun 2010 15:05:23 -0700 (PDT) Gabor <gabor(a)alacron.com> wrote: (...) > Also if you have severe problems, like it looks like > nothing works at all, you could have a loop in the > reset generation logic. Remember that the output of > a DCM does not toggle until locked, so using it to > release reset to the DCM will lock up the system > because the reset prevents the DCM from locking. > > Regards, > Gabor To follow on with the DCM feature, performing an initial DCM reset with the timings in compliance with the user-guide and datasheet is a must (with special care when dealing with early Virtex-4 revisions, altough it is not the case here). I suggest to the OP that he should focus on verifying the obvious (pwr-supply levels, input clock waveform, pin-mapping, UCF file, JTAG connection, DCM lock and status outputs). -- Matthieu Michon <prenom.nom(a)gmail.com>
From: maxascent on 10 Jun 2010 04:24 If you are convinced that your simulation of the design is correct then you really need to use Chipscope to see what is going on inside the device. Jon --------------------------------------- Posted through http://www.FPGARelated.com
From: BrandonD on 10 Jun 2010 06:28 I am getting some warnings during post-par simulation that may be a clue. When I load my routed design in Modelsim, I am getting 14 warnings like this for different nets: Instance 'top.fab.\fs1/ras/reset_n_inv_shift1 ' - No solution possible for delayed timing check nets. Setting negative limit to zero. In the static timing report for the OFFSET IN BEFORE timing constraint (which I have not set so it must be determined by ISE) I have a total minimum clock path delay of -0.678 ns. For the OFFSET OUT AFTER constraint I have a maximum clock path delay of -0.256 ns. I wasn't sure if this meant something as the path for these delays are from the input clock buffer to the DCM. I don't believe the warnings in the simulation are normal but are negative delay values normal? Thanks, Brandon >If you are convinced that your simulation of the design is correct then you >really need to use Chipscope to see what is going on inside the device. > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.com
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