Design passes synthesis and routing but fails on FPGA
in [FPGA]
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From: BrandonD on 9 Jun 2010 11:01 Hi, I'm somewhat familiar with synthesis and Verilog but I am quite new to running the designs on FPGAs. I have a complex design of a processor that I am trying to get running on a Virtex 5 FPGA in a BEE3 module. The design synthesizes and goes through translate, map and par in Xilinx ISE 10.1 but it does not seem to run correctly when programmed on the FPGA. ISE says that all timing constraints have been met and the static timing report shows that it does too. What I am going to do now is look at the post-par simulation and see if there's a problem. Is there anything that maybe is a common mistake that I should also look into? I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. Any suggestions will be appreciated. Thanks, Brandon --------------------------------------- Posted through http://www.FPGARelated.com
From: Rob Gaddi on 9 Jun 2010 12:29 On 6/9/2010 8:01 AM, BrandonD wrote: > Hi, > > I'm somewhat familiar with synthesis and Verilog but I am quite new to > running the designs on FPGAs. I have a complex design of a processor that I > am trying to get running on a Virtex 5 FPGA in a BEE3 module. The design > synthesizes and goes through translate, map and par in Xilinx ISE 10.1 but > it does not seem to run correctly when programmed on the FPGA. > > ISE says that all timing constraints have been met and the static timing > report shows that it does too. What I am going to do now is look at the > post-par simulation and see if there's a problem. Is there anything that > maybe is a common mistake that I should also look into? > > I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. Any > suggestions will be appreciated. > > Thanks, > Brandon > > > > --------------------------------------- > Posted through http://www.FPGARelated.com Anything other than single clock synchronous logic isn't represented in your timing constraints; so anywhere that you're using a clock other than your derived 50 is worth another look. This includes any logic running off of a combinationally gated clock. You said you're used to synthesis but not FPGAs; if that means ASICs then one thing to be aware of is that clock nets are a lot more sacred in FPGAs. Unless you've specified your external OFFSET IN/OUT constraints properly (this is rare), then your constraints don't properly cover your relationships to external hardware. Worth another look. -- Rob Gaddi, Highland Technology Email address is currently out of order
From: BrandonD on 9 Jun 2010 12:45 By being familiar with synthesis, I mean I'm a student and have had some coursework with the design and synthesis, but projects ended there. To be honest, they were more on the design aspect so I am familiar with the synthesis process but not too experienced with it. I do not use any gated clocks and all of my sequential logic runs of the same edge of the same 50 MHz clock except for the reset logic when the DCM is stabilizing. I have not set any OFFSET IN/OUT constraints, do you know where I can get more information about doing that? Thanks, Brandon >On 6/9/2010 8:01 AM, BrandonD wrote: >> Hi, >> >> I'm somewhat familiar with synthesis and Verilog but I am quite new to >> running the designs on FPGAs. I have a complex design of a processor that I >> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The design >> synthesizes and goes through translate, map and par in Xilinx ISE 10.1 but >> it does not seem to run correctly when programmed on the FPGA. >> >> ISE says that all timing constraints have been met and the static timing >> report shows that it does too. What I am going to do now is look at the >> post-par simulation and see if there's a problem. Is there anything that >> maybe is a common mistake that I should also look into? >> >> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. Any >> suggestions will be appreciated. >> >> Thanks, >> Brandon >> >> >> >> --------------------------------------- >> Posted through http://www.FPGARelated.com > >Anything other than single clock synchronous logic isn't represented in >your timing constraints; so anywhere that you're using a clock other >than your derived 50 is worth another look. This includes any logic >running off of a combinationally gated clock. You said you're used to >synthesis but not FPGAs; if that means ASICs then one thing to be aware >of is that clock nets are a lot more sacred in FPGAs. > >Unless you've specified your external OFFSET IN/OUT constraints properly >(this is rare), then your constraints don't properly cover your >relationships to external hardware. Worth another look. > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order > --------------------------------------- Posted through http://www.FPGARelated.com
From: BrandonD on 9 Jun 2010 15:15 By being familiar with synthesis, I mean I'm a student and have had some coursework with the design and synthesis, but projects ended there. To be honest, they were more on the design aspect so I am familiar with the synthesis process but not too experienced with it. I do not use any gated clocks and all of my sequential logic runs of the same edge of the same 50 MHz clock except for the reset logic when the DCM is stabilizing. I have not set any OFFSET IN/OUT constraints, do you know where I can get more information about doing that? Thanks, Brandon >On 6/9/2010 8:01 AM, BrandonD wrote: >> Hi, >> >> I'm somewhat familiar with synthesis and Verilog but I am quite new to >> running the designs on FPGAs. I have a complex design of a processor that I >> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The design >> synthesizes and goes through translate, map and par in Xilinx ISE 10.1 but >> it does not seem to run correctly when programmed on the FPGA. >> >> ISE says that all timing constraints have been met and the static timing >> report shows that it does too. What I am going to do now is look at the >> post-par simulation and see if there's a problem. Is there anything that >> maybe is a common mistake that I should also look into? >> >> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. Any >> suggestions will be appreciated. >> >> Thanks, >> Brandon >> >> >> >> --------------------------------------- >> Posted through http://www.FPGARelated.com > >Anything other than single clock synchronous logic isn't represented in >your timing constraints; so anywhere that you're using a clock other >than your derived 50 is worth another look. This includes any logic >running off of a combinationally gated clock. You said you're used to >synthesis but not FPGAs; if that means ASICs then one thing to be aware >of is that clock nets are a lot more sacred in FPGAs. > >Unless you've specified your external OFFSET IN/OUT constraints properly >(this is rare), then your constraints don't properly cover your >relationships to external hardware. Worth another look. > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order > --------------------------------------- Posted through http://www.FPGARelated.com
From: Gabor on 9 Jun 2010 18:05 On Jun 9, 12:45 pm, "BrandonD" <BdOn003(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > By being familiar with synthesis, I mean I'm a student and have had some > coursework with the design and synthesis, but projects ended there. To be > honest, they were more on the design aspect so I am familiar with the > synthesis process but not too experienced with it. > > I do not use any gated clocks and all of my sequential logic runs of the > same edge of the same 50 MHz clock except for the reset logic when the DCM > is stabilizing. > > I have not set any OFFSET IN/OUT constraints, do you know where I can get > more information about doing that? > > Thanks, > Brandon > > > > > > >On 6/9/2010 8:01 AM, BrandonD wrote: > >> Hi, > > >> I'm somewhat familiar with synthesis and Verilog but I am quite new to > >> running the designs on FPGAs. I have a complex design of a processor > that I > >> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The > design > >> synthesizes and goes through translate, map and par in Xilinx ISE 10.1 > but > >> it does not seem to run correctly when programmed on the FPGA. > > >> ISE says that all timing constraints have been met and the static > timing > >> report shows that it does too. What I am going to do now is look at the > >> post-par simulation and see if there's a problem. Is there anything > that > >> maybe is a common mistake that I should also look into? > > >> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock. > Any > >> suggestions will be appreciated. > > >> Thanks, > >> Brandon > > >> --------------------------------------- > >> Posted throughhttp://www.FPGARelated.com > > >Anything other than single clock synchronous logic isn't represented in > >your timing constraints; so anywhere that you're using a clock other > >than your derived 50 is worth another look. This includes any logic > >running off of a combinationally gated clock. You said you're used to > >synthesis but not FPGAs; if that means ASICs then one thing to be aware > >of is that clock nets are a lot more sacred in FPGAs. > > >Unless you've specified your external OFFSET IN/OUT constraints properly > >(this is rare), then your constraints don't properly cover your > >relationships to external hardware. Worth another look. > > >-- > >Rob Gaddi, Highland Technology > >Email address is currently out of order > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com You may want to look at the "blogs" section of the Xilinx web forums. There is a 5-part piece on timing constraints that is quite useful when you're getting started. Also if you have severe problems, like it looks like nothing works at all, you could have a loop in the reset generation logic. Remember that the output of a DCM does not toggle until locked, so using it to release reset to the DCM will lock up the system because the reset prevents the DCM from locking. Regards, Gabor
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