Does anyone ever use placement? [FPGA]

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From: Steve Ravet on 5 Nov 2009 14:56

Do any of you advanced users ever use the floorplanning tools to do
placement? I'm not talking about placing clock buffers or other individual
items, I'm talking about ASIC style floorplanning for units and sub-units.
I've asked AE's about that and the response is always to let the tool do
placement. So I'm asking experts: Do you ever floorplan, and if so why?
To speed up map? To help with timing? Thanks for any insight,

--steve

From: Gabor on 5 Nov 2009 16:04

From: Nico Coesel on 5 Nov 2009 18:18

Gabor <gabor(a)alacron.com> wrote:

>On Nov 5, 2:56=A0pm, "Steve Ravet" <steve.ra...(a)arm.com> wrote:
>> Do any of you advanced users ever use the floorplanning tools to do
>> placement? =A0I'm not talking about placing clock buffers or other indivi=
>dual
>> items, I'm talking about ASIC style floorplanning for units and sub-units=
>.
>> I've asked AE's about that and the response is always to let the tool do
>> placement. =A0So I'm asking experts: =A0Do you ever floorplan, and if so =
>why?
>> To speed up map? =A0To help with timing? =A0Thanks for any insight,
>>
>> --steve
>
>My approach is let the tools run, and if they fail miserably
>(generally only a matter of meeting timing, not completing
>routing) then see how I can help them along. I had a fairly
>full Virtex 2 design and had some issues with timing. This was
>before Xilinx picked up PlanAhead and I tried the PlanAhead tool
>from HierDesign. I found that at least in my case PlanAhead
>actually made matters worse than just letting the tools place
>anything anywhere. I imagine there are some more highly-
>structured designs where this would not be the case. About
>the only other thing I do is place block RAM's when I find that
>the tools are not placing them efficiently. My experience has
>been that the general FPGA fabric is best placed by the tools.

I had to do that once but I used the constraints to force the location
of a block RAM. That improved timing considerably.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

From: rickman on 5 Nov 2009 19:28

On Nov 5, 2:56 pm, "Steve Ravet" <steve.ra...(a)arm.com> wrote:
> Do any of you advanced users ever use the floorplanning tools to do
> placement? I'm not talking about placing clock buffers or other individual
> items, I'm talking about ASIC style floorplanning for units and sub-units.
> I've asked AE's about that and the response is always to let the tool do
> placement. So I'm asking experts: Do you ever floorplan, and if so why?
> To speed up map? To help with timing? Thanks for any insight,

Floorplanning is a major PITA, not from the perspective of the tools
not being easy to use (although I don't make any claims to the
contrary either) but just from a development perspective. To use
floorplanning you need to add a fairly messy/complex step to your
process in order to get a design you can test. This has to be
repeated each time you make a change, at least on the part changed. A
small change to an HDL design can often result in much larger changes
to the implementation due to optimizations.

I can't say any of this for certain since I have not needed to
floorplan for almost a decade and I am sure the tools are better. I
believe at least Xilinx has some incremental compile feature which
should help to minimize the extent of changes due to a design change.
That would help, but it still remains a messy proposition.

I know there are some people who use floorplanning regularly, Ray
Andraka for one. He started with FPGAs back when we used schematic
for entry. He had built up a large library of schematic functional
blocks with hierarchical placement properties which allowed him to
floorplan an entire design. I believe he resisted HDL for some time
because he thought he would loose this investment. After his
customers insisted that he use VHDL (government I believe) he looked
at it with a critical eye, tried some test cases with support from
Xilinx (his is mainly a Xilinx house) and found he could use the same
placement features by instantiating the same sort of functional and
primitive elements. So I believe this has worked out very well for
him, especially since HDL also adds a lot of benefit from being text
based rather than requiring a particular product for the schematics.

The bottom line, yes, you can do projects with floorplanning which
will help with both fitting and speed in a design, especially if it
has repeating units. But it is a long row to hoe and works best if
you will be using this process repeatedly to amortize the learning
curve costs as well as take advantage of design reuse that is
possible. But if your project doesn't *require* it, why bother?

Rick

From: Kim Enkovaara on 6 Nov 2009 01:41

rickman wrote:
> I can't say any of this for certain since I have not needed to
> floorplan for almost a decade and I am sure the tools are better. I
> believe at least Xilinx has some incremental compile feature which
> should help to minimize the extent of changes due to a design change.
> That would help, but it still remains a messy proposition.

My biggest problem is that the Xilinx placer is horribly bad. It seems
to place everything at random and then just hopes that it might be
able to meet the timing and route the mess. Of course if you have
time just run all the different seeds for the placement, one of them
might be good enough guess ;) Manual placement of the memories usually
helps a lot.

My own feeling is that the Altera placer is better than the Xilinx
altough it also has some problems with the different size memories
(M144k vs M9k etc.).

Fortunately there are physical synthesis tools for FPGAs from
3rd parties, they at least make reasonable placement for the FPGA
tools to start their work.

--Kim

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