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From: Morppheu on 11 Jan 2010 11:22
Hey guys...

I need a little help with my E1 interface.
I have an internal clock and the E1 clock. When E1 chip (MT9076B) is
present I use the E1 clock + E1 F0 signals, else I use the internal
clock.
I want to use a DCM to lock the phase of internal clock (4.096MHz)
with the E1 external clock. Is it possible?
Today I have a process to detect if E1 F0 signals is present. If its
present, I switch from internal clock to E1 clock :
clk_res <= clk_int when E1_present = 0 else clk_e1;

I know its a very bad design technique, but its an old code from
another guy and I am looking to make the things right.
What is the best way to interface with E1?

Can someone help me?

Thanks!
From: Nico Coesel on 11 Jan 2010 15:08
Morppheu <jdemamann(a)gmail.com> wrote:

>Hey guys...
>
>I need a little help with my E1 interface.
>I have an internal clock and the E1 clock. When E1 chip (MT9076B) is
>present I use the E1 clock + E1 F0 signals, else I use the internal
>clock.

Why use the internal clock? Isn't the MT9076 free running when it
doesn't see a line-sync?

>I know its a very bad design technique, but its an old code from
>another guy and I am looking to make the things right.
>What is the best way to interface with E1?

Many years ago I did a design using the MT9075. I let its internal PLL
deal with the E1 clock.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: Morppheu on 12 Jan 2010 09:00
> Why use the internal clock? Isn't the MT9076 free running when it
> doesn't see a line-sync?

Yes, the MT goes free running when its not sinced.
But the MT9076 is a module on my hardware. I can mount the backplane
with or without the MT9076 chip.
That is the point, what to do when I have the E1 module installed. How
to interface with it.
My FPGA is an Spartan 3e S100 (almost 100% full):

Logic Utilization:
Total Number Slice Registers: 737 out of 1,920 38%
Number used as Flip Flops: 731
Number used as Latches: 6
Number of 4 input LUTs: 956 out of 1,920 49%
Logic Distribution:
Number of occupied Slices: 959 out of
960 99%
Number of Slices containing only related logic: 959 out of
959 100%
Number of Slices containing unrelated logic: 0 out of
959 0%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number of 4 input LUTs: 1,910 out of 1,920 99%
Number used as logic: 956
Number used as a route-thru: 181
Number used for Dual Port RAMs: 768
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 5
Number of bonded IOBs: 93 out of 108 86%
IOB Flip Flops: 19
Number of Block RAMs: 4 out of 4 100%
Number of GCLKs: 9 out of 24 37%
Number of DCMs: 2 out of 2 100%

Another thing. How to reduce the area usage??

Thanks!
From: Nico Coesel on 12 Jan 2010 13:18
Morppheu <jdemamann(a)gmail.com> wrote:

>> Why use the internal clock? Isn't the MT9076 free running when it
>> doesn't see a line-sync?
>
>Yes, the MT goes free running when its not sinced.

That is not a problem. Just use that clock always.

>But the MT9076 is a module on my hardware. I can mount the backplane
>with or without the MT9076 chip.

I guess the logic is idle when the module is not mounted. Pulling the
clock down or up to have a defined logic level should do it.

>That is the point, what to do when I have the E1 module installed. How
>to interface with it.
>My FPGA is an Spartan 3e S100 (almost 100% full):
>
>Logic Utilization:
> Total Number Slice Registers: 737 out of 1,920 38%
> Number used as Flip Flops: 731
> Number used as Latches: 6
> Number of 4 input LUTs: 956 out of 1,920 49%
>Logic Distribution:
> Number of occupied Slices: 959 out of
>960 99%
> Number of Slices containing only related logic: 959 out of
>959 100%
> Number of Slices containing unrelated logic: 0 out of
>959 0%
> *See NOTES below for an explanation of the effects of unrelated
>logic
>Total Number of 4 input LUTs: 1,910 out of 1,920 99%
> Number used as logic: 956
> Number used as a route-thru: 181
> Number used for Dual Port RAMs: 768
> (Two LUTs used per Dual Port RAM)
> Number used as Shift registers: 5
> Number of bonded IOBs: 93 out of 108 86%
> IOB Flip Flops: 19
> Number of Block RAMs: 4 out of 4 100%
> Number of GCLKs: 9 out of 24 37%
> Number of DCMs: 2 out of 2 100%
>
>Another thing. How to reduce the area usage??

Almost half the LUTs are used as dual port rams. Perhaps an
inefficient FIFO for audio/D channel? I'd use boundary crossing
registers instead of a FIFO.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: rickman on 13 Jan 2010 10:35
I'm not sure where this thread started, I don't see a message before
Nico's post Jan 11. Did you post your code?

Your design is using about 10% of the LUTs as routing, which does tend
to happen when your LUT usage rises using up much of the routing
resources. The main offender that I can see is the use of almost 50%
of the LUTs as DP RAM. I am guessing that these are being used for
FIFO buffers. Can you reduce the number of LUTs used for buffering or
are they all required?

As to the clocking issue, I don't know what the problem is exactly.
Why can't you use the E1 clock? What pin is the E1 clock connected to
on the S3 part? I would hope it is connected to a DCM or at least a
clock input.

It is hard to suggest much more without more insight into what your
design is doing.

Rick


On Jan 12, 9:00 am, Morppheu <jdemam...(a)gmail.com> wrote:
> > Why use the internal clock? Isn't the MT9076 free running when it
> > doesn't see a line-sync?
>
> Yes, the MT goes free running when its not sinced.
> But the MT9076 is a module on my hardware. I can mount the backplane
> with or without the MT9076 chip.
> That is the point, what to do when I have the E1 module installed. How
> to interface with it.
> My FPGA is an Spartan 3e S100 (almost 100% full):
>
> Logic Utilization:
>   Total Number Slice Registers:       737 out of   1,920   38%
>     Number used as Flip Flops:                   731
>     Number used as Latches:                        6
>   Number of 4 input LUTs:             956 out of   1,920   49%
> Logic Distribution:
>   Number of occupied Slices:                          959 out of
> 960   99%
>     Number of Slices containing only related logic:     959 out of
> 959  100%
>     Number of Slices containing unrelated logic:          0 out of
> 959    0%
>       *See NOTES below for an explanation of the effects of unrelated
> logic
> Total Number of 4 input LUTs:          1,910 out of   1,920   99%
>   Number used as logic:                956
>   Number used as a route-thru:         181
>   Number used for Dual Port RAMs:      768
>     (Two LUTs used per Dual Port RAM)
>   Number used as Shift registers:        5
>   Number of bonded IOBs:               93 out of     108   86%
>     IOB Flip Flops:                    19
>   Number of Block RAMs:                4 out of       4  100%
>   Number of GCLKs:                     9 out of      24   37%
>   Number of DCMs:                      2 out of       2  100%
>
> Another thing. How to reduce the area usage??
>
> Thanks!

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