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From: JPS Nagi on 27 Sep 2006 21:10
Hi All,

The EC/ECP EBR (or Block RAM) can be configured in the following modes
(as supported in the hardware):
- Single Port RAM (RAM_DQ)
- Dual Port RAM (RAM_DP)
- True Dual Port RAM (RAM_DP_TRUE)
- Read Only Memory (ROM)

The EBR block does not have a native hardware support for the FIFO. The
way FIFO is created for the EC/ECP devices is by utilizing a Dual port
RAM (RAM_DP) and then adding the address counters and the flag logic.

The IP Express tool in ispLEVER is fully capable of creating both a
single clock FIFO and a Dual Clock FIFO (FIFO_DC). It is emulated FIFO
that utilizes RAM_DP underneath.

Besides using the IP Express tool, another way to implement RAMs in the
EC/ECP devices is by inferencing them i.e. you write a behavioral VHDL
or Verilog code for the memory style and the synthesis tool
automatically implements the RAM.

By default, ispLEVER uses the following criteria:

+ If the inferenced memory is smaller than 2K bits, use the PFU's
(or slices) and implement a Distributed RAM (Single, Dual or True Dual
Port) or ROM.

+ If the inferenced memory is larger than 2K bits, use the Block RAM
and implement an EBR based RAM (Single, Dual or True Dual Port RAM) or
ROM.


The attribute that is being discussed and questioned in this thread is
the Synplify attribute "syn_ramstyle".

This attribute comes in handy when you are inferencing a memory and you
want to force the synthesis to implement it using either the EBR blocks
or the Slices.

Now, the FIFO in the Ben Cohen's book. It is a FIFO infrencing example.
And since there is no FIFO support in the hardware, the software
implements it as logic and not RAM, since it can not be mapped to the
four RAM modes listed above.

And thus uses the slices to implement the FIFO making the attribute
"syn_ramstyle" ineffective.

This would happen in both EC/ ECP/ XP families from Lattice as the FIFO
is emulated in these devices.

I hope this clarifies why the attribute is not working.

Regards
JP Singh

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