ddr2 sodimm controller [FPGA]

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From: waishanl on 27 Sep 2006 18:50

Hi! i am having problem to communicate between virtex4 fx60 to 512
SODIMM. I use the MIG1.6 to generate a controller. I add one module
into the design, change some names and run ModelSim. The simulation
looks fine. So, i use the ICE tools to get my bit file. When i check
all the report, I saw the map report have the follwoing message:

WARNING:MapLib:851 - Your design is using FIFO16 primitives, Please
note that
there are additional requirements for the FIFO16 to guarantee full
functionality. For more information regarding requirements for the
FIFO16
primitive, please see Answer Record 22462.

is that going to cause me fail on the design? I didn't fine any .edn or
ngc file in the folder that MIG generate.

I also run the time simulation, it didn't match with the funcational
simulation. Seems like signal start fail in 200ns. Am i missing
anything?

In addition, I chipscope the signal. It seems like data did get in the
fifo. But the controller never request a read. Any ideas?

Thanks!
Wai Shan

From: Joseph Samson on 27 Sep 2006 20:47

waishanl(a)gmail.com wrote:
> Hi! i am having problem to communicate between virtex4 fx60 to 512
> SODIMM. I use the MIG1.6 to generate a controller. I add one module
> into the design, change some names and run ModelSim. The simulation
> looks fine. So, i use the ICE tools to get my bit file. When i check
> all the report, I saw the map report have the follwoing message:
>
> WARNING:MapLib:851 - Your design is using FIFO16 primitives, Please
> note that
> there are additional requirements for the FIFO16 to guarantee full
> functionality. For more information regarding requirements for the
> FIFO16
> primitive, please see Answer Record 22462.
>
> is that going to cause me fail on the design? I didn't fine any .edn or
> ngc file in the folder that MIG generate.
>
> I also run the time simulation, it didn't match with the funcational
> simulation. Seems like signal start fail in 200ns. Am i missing
> anything?
>
> In addition, I chipscope the signal. It seems like data did get in the
> fifo. But the controller never request a read. Any ideas?

There has been quite a bit written lately about DDR2 and MIG in this
newsgroup. Search for ddr2 and MIG. I recommend replacing the FIFO16s
with FIFOs generated by CoreGen that don't use the FIFO16 primitive. I
had problems with the address/command FIFO. It would be empty, but still
indicate that it had data, so the same memory cycle would run forever.

---
Joe Samson
Pixel Velocity

From: waishanl on 28 Sep 2006 20:16

I think the FIFO16 is not the killer of the simulation. i saw the empty
flag and full flag toggle. I run the the synthesis by xst and
precision. and generate the time simulation model and see the
difference. Here is the error send by the memory model.

time simulation model create by using precision as synthesis, i got the
following error:
# ddr2_test_tb.X16_0_7.cmd_addr_timing_check: at time 208548390.0 ps
ERROR: tIH violation on ADDR 10 by 304.0 ps
# ddr2_test_tb.X16_0_0.main: at time 208548403.0 ps ERROR: tIS
violation on ADDR 10 by 237.0 ps

i got lots of them then it just stop the simulation.

time simulation model create by using xst as synthesis, i got the
following error:
# ddr2_test_tb.X16_0_7.cmd_addr_timing_check: at time 208548373.0 ps
ERROR: tIH violation on RAS_N by 319.0 ps
# ddr2_test_tb.X16_0_6.cmd_addr_timing_check: at time 208548373.0 ps
ERROR: tIH violation on RAS_N by 319.0 ps
# ddr2_test_tb.X16_0_5.cmd_addr_timing_check: at time 208548373.0 ps
ERROR: tIH violation on RAS_N by 319.0 ps
# ddr2_test_tb.X16_0_4.cmd_addr_timing_check: at time 208548373.0 ps
ERROR: tIH violation on RAS_N by 319.0 ps
# ddr2_test_tb.X16_0_0.main: at time 208548399.0 ps ERROR: tIS
violation on RAS_N by 224.0 ps

i also try to look at internal signal. cinflict_detect,
ctrl_dummy_wr_sel, ctrl_dummyread_start never went high. The init_count
is 1.

Do anyone have some idea that make the controller working.

Thanks!
Wai Shan

Joseph Samson wrote:
> waishanl(a)gmail.com wrote:
> > Hi! i am having problem to communicate between virtex4 fx60 to 512
> > SODIMM. I use the MIG1.6 to generate a controller. I add one module
> > into the design, change some names and run ModelSim. The simulation
> > looks fine. So, i use the ICE tools to get my bit file. When i check
> > all the report, I saw the map report have the follwoing message:
> >
> > WARNING:MapLib:851 - Your design is using FIFO16 primitives, Please
> > note that
> > there are additional requirements for the FIFO16 to guarantee full
> > functionality. For more information regarding requirements for the
> > FIFO16
> > primitive, please see Answer Record 22462.
> >
> > is that going to cause me fail on the design? I didn't fine any .edn or
> > ngc file in the folder that MIG generate.
> >
> > I also run the time simulation, it didn't match with the funcational
> > simulation. Seems like signal start fail in 200ns. Am i missing
> > anything?
> >
> > In addition, I chipscope the signal. It seems like data did get in the
> > fifo. But the controller never request a read. Any ideas?
>
> There has been quite a bit written lately about DDR2 and MIG in this
> newsgroup. Search for ddr2 and MIG. I recommend replacing the FIFO16s
> with FIFOs generated by CoreGen that don't use the FIFO16 primitive. I
> had problems with the address/command FIFO. It would be empty, but still
> indicate that it had data, so the same memory cycle would run forever.
>
> ---
> Joe Samson
> Pixel Velocity

From: waishanl on 28 Sep 2006 20:18

From: waishanl on 28 Sep 2006 20:23

Joseph Samson wrote:
> waishanl(a)gmail.com wrote:
> > Hi! i am having problem to communicate between virtex4 fx60 to 512
> > SODIMM. I use the MIG1.6 to generate a controller. I add one module
> > into the design, change some names and run ModelSim. The simulation
> > looks fine. So, i use the ICE tools to get my bit file. When i check
> > all the report, I saw the map report have the follwoing message:
> >
> > WARNING:MapLib:851 - Your design is using FIFO16 primitives, Please
> > note that
> > there are additional requirements for the FIFO16 to guarantee full
> > functionality. For more information regarding requirements for the
> > FIFO16
> > primitive, please see Answer Record 22462.
> >
> > is that going to cause me fail on the design? I didn't fine any .edn or
> > ngc file in the folder that MIG generate.
> >
> > I also run the time simulation, it didn't match with the funcational
> > simulation. Seems like signal start fail in 200ns. Am i missing
> > anything?
> >
> > In addition, I chipscope the signal. It seems like data did get in the
> > fifo. But the controller never request a read. Any ideas?
>
> There has been quite a bit written lately about DDR2 and MIG in this
> newsgroup. Search for ddr2 and MIG. I recommend replacing the FIFO16s
> with FIFOs generated by CoreGen that don't use the FIFO16 primitive. I
> had problems with the address/command FIFO. It would be empty, but still
> indicate that it had data, so the same memory cycle would run forever.
>
> ---
> Joe Samson
> Pixel Velocity

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