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From: DougW on 7 Apr 2010 21:37
>On Dec 23, 11:15 am, Gabor <ga...(a)alacron.com> wrote:
>> On Dec 23, 1:50 am, "Andrew W. Hill" <aquaregi...(a)gmail.com> wrote:
>> > I'm using EDK 10.1, specced for the ML501. When I reach the mapping
>> > phase, I get the following error (several times):
>>
>> > ERROR:PhysDesignRules:1492 - Incompatible programming for comp
>> > mb_plb_M_ABus<1>.
>> > The pair of luts SLICEL_A5LUT and SLICEL_A6LUT must have a
>> > compatible
>> > equation, lower bits must be programmed the same. The SLICEL_A5LUT
>> > hex
>> > equation is <O5=0x08080808> and the SLICEL_A6LUT hex equation is
>> > <O6=0x607AA67800008888>.
>>
>> > I found the following Xilinx note on the error, which notes that this
>> > error was erroneously thrown in EDK versions <8
:http://www.xilinx.com/support/answers/23645.htm
>>
>> > My system is fairly standard. I used BSB and added a few things
>> > (LEDs,switches), but nothing particularly exotic. Is there something
>> > obvious that I might have missed, or is this likely to be an error
>> > with DRC?
>>
>> The obvious question, given the note from Xilinx, is did you ever
>> build
>> any part of this system under an older revision of EDK? Xilinx
>> software
>> is famous for failing to clean up old bits of object...
>
>I previously built under EDK 9, but I did a clean from within EDK and
>also did a quick walkthrough of the remaining files. I've never built
>it in EDK <8.
>Cheers
>Andrew
>

I got the same error message. "Incompatible programming for comp
mb_plb_M_Abus<29>". After installing the service pack 3 for ISE, this
problem went away.

-Doug W



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