Summing with carry problems ...
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From: Kappa on 8 Apr 2010 04:30 Hi, again me ... :-) ... I have one problem with SUM of 3 signal. ############# [CODE]############# signal E : std_logic_vector (3 downto 0); signal Z : std_logic_vector (3 downto 0); signal r : std_logic; signal total : std_logic_vector(4 downto 0); total <= Zi + Ei + r; ############# [/CODE]############# If I generate the block schematic (Xilinx ISE) the "adder" have 2 input of 4 bits and CI, and so far are perfectly okay, but the output is 4 bits without CO ... why ? Where he finished 5th bit of total signal ? Where is that wrong ? I'm confused ... secureasm
From: Kappa on 8 Apr 2010 04:59 Add a notes, infact I receiving a warning from tools: "Width mismatch. <total> has a width of 5 bits but assigned expression is 4-bit wide." I have used alse this template (for adder with carry out) but without resul : <temp_value> <= <input1> + <input2>; <output_sum> <= <temp_value>((<adder_width>-1) downto 0); <carry_out> <= <temp_value>(<adder_width>); How generate adder with carry out ? secureasm
From: whygee on 8 Apr 2010 05:22 Kappa wrote: > Add a notes, infact I receiving a warning from tools: > > "Width mismatch. <total> has a width of 5 bits but assigned expression > is 4-bit wide." > > I have used alse this template (for adder with carry out) but without > resul : > > <temp_value> <= <input1> + <input2>; > <output_sum> <= <temp_value>((<adder_width>-1) downto 0); > <carry_out> <= <temp_value>(<adder_width>); > > How generate adder with carry out ? > > secureasm one way I have used : implement a "normal" adder, with 1 more MSB and one more LSB, so you have tmp : std_logic_vector(width+1 downto 0); then : you construct your 2 operands so that - the LSB is the carry in, it goes on one input, the other input is stuck to '1' => carry in propagates to the next LSB. - The MSB is the carry out. - the other bits are the normal wide operands. I did this on http://yasep.org/VHDL/ASU_ROP2_16.vhd and the result code is : -- add/sub : sumAux := unsigned('0' & ActualAr & '1') + unsigned('0' & ActualBr & Addsubr); -- if (Addsub = '0') then + else - modulo some variable renaming, of course, and the temporary result sumAux here is a unsigned, it is cast later as a std_logic_vector : -- trim the LSB (carry-in) Sum(Sum'left downto 0) <= std_ulogic_vector(sumAux(sumAux'left downto 1)); It should work everywhere and the unnecessary bits must be optimised out. HTH yg -- http://ygdes.com / http://yasep.org
From: KJ on 8 Apr 2010 07:56 On Apr 8, 4:30 am, Kappa <secure...(a)gmail.com> wrote: > Hi, again me ... :-) ... > > I have one problem with SUM of 3 signal. > > ############# [CODE]############# > > signal E : std_logic_vector (3 downto 0); > signal Z : std_logic_vector (3 downto 0); > signal r : std_logic; > signal total : std_logic_vector(4 downto 0); > > total <= Zi + Ei + r; > > ############# [/CODE]############# > > If I generate the block schematic (Xilinx ISE) the "adder" have 2 > input of 4 bits and CI, and so far are perfectly okay, but the output > is 4 bits without CO ... why ? > Does total(4) get used anywhere? If not, then it will get optimized away since it is not needed. > Where he finished 5th bit of total signal ? > You tell us, the use of total(4) would be in your code. Any signal that does cause an output pin to change either directly, or indirectly, will get optimized away. > Where is that wrong ? > Your expectations are likely what is wrong. > I'm confused ... > Try bringing total(4) to an output pin. KJ
From: Symon on 8 Apr 2010 11:38
This doesn't answer your question per se, but is worth reading. http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf You are using ieee.numeric_std.all ? You should be! HTH., Syms. |