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From: Pravin on 26 Jul 2010 05:32
Hi,

I'm interfacing Actel FPGA with Freescale Coldfire Processor. This
interface is operating @ 75Mhz.
FPGA output signal (TA -Transfer acknowledge) and FPGA data out is
sampled at rising edge by Processor.

As per Coldfire Processor datasheet, setup time for this signals is
9ns and 0ns is hold time.

I am giving constraints as follows.

#Period constraint
create_clock -name { i_PROC_CLKOUT } -period 13.333 -waveform { 0.000
6.667 } { i_PROC_CLKOUT }

set_input_delay 11.667 -clock { i_PROC_CLKOUT } [get_ports
{ i_PROC_CS1n }]

# adding 1ns to account PCB trace delay
set_output_delay 10.000 -clock { i_PROC_CLKOUT } [get_ports
{ o_PROC_TAn }]

Here if I just delay my input signal and connected to output pin, my
timings are not met (slack is -4.745ns).

How do operate the design (glue logic) at 75MHz without any timing
violations?

always @(posedge i_PROC_CLKOUT or negedge i_RESETn)
begin
if(i_RESETn == 1'b0)
r_sync_proc_cs1n <= 1'b1;
else
r_sync_proc_cs1n <= i_PROC_CS1n ;
end
assign o_PROC_TAn = r_sync_proc_cs1n;

Thanks in advance.
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