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From: -jg on 6 Mar 2010 15:55 On Mar 6, 8:10 am, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > Peter Alfke <al...(a)sbcglobal.net> wrote: > > (snip) > > > Peter Alfke, formerly Xilinx Applications (some of you may remember me) > > and also notice that you don't post as often as before. > > I was not so long ago thinking of asking: > > There is picoblaze (8 bit), and microblaze (32 bit), but no > nanoblaze (16 bit) or milliblaze (64 bit). It might even > be interesting to have a femtoblaze (4 bit) processor. There is a newish 4 bit core here, that could be a template ? GC49C50x series http://www.coreriver.co.kr/product-lines/top_corerivermcu.html Atom summary: # CPU - 4-bit reduced 8051 architecture - Continuous program addressing, not paged. - 51 instructions including push, pop and logic inst. - Instruction cycle : fSYS/6 - Multi-level subroutine nesting with RAM based stack. # On-chip Memories : - FLASH : 1024 Bytes (including EEPROM : 128 Bytes ) - RAM : 64 nibbles (including stack) It could also be timely for someone to target the new QuadSPI Flash to a FPGA core. Code memory is always the achilles heel of Soft-CPU. -jg
From: Antti on 6 Mar 2010 16:06 On Mar 6, 10:55 pm, -jg <jim.granvi...(a)gmail.com> wrote: > On Mar 6, 8:10 am, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > > > Peter Alfke <al...(a)sbcglobal.net> wrote: > > > (snip) > > > > Peter Alfke, formerly Xilinx Applications (some of you may remember me) > > > and also notice that you don't post as often as before. > > > I was not so long ago thinking of asking: > > > There is picoblaze (8 bit), and microblaze (32 bit), but no > > nanoblaze (16 bit) or milliblaze (64 bit). It might even > > be interesting to have a femtoblaze (4 bit) processor. > > There is a newish 4 bit core here, that could be > a template ? GC49C50x serieshttp://www.coreriver.co.kr/product-lines/top_corerivermcu.html > > Atom summary: > # CPU > - 4-bit reduced 8051 architecture > - Continuous program addressing, not paged. > - 51 instructions including push, pop and logic inst. > - Instruction cycle : fSYS/6 > - Multi-level subroutine nesting with RAM based stack. > # On-chip Memories : > - FLASH : 1024 Bytes (including EEPROM : 128 Bytes ) > - RAM : 64 nibbles (including stack) > > It could also be timely for someone to target the > new QuadSPI Flash to a FPGA core. > Code memory is always the achilles heel of Soft-CPU. > > -jg Jim, 1) the 4-bit "Atom" isnt so new ;) 2) NanoBlaze is registered trademark of Xilinx hm... one of my softcores has been pushed into useable status its small core that is optimized to run from one single block ram and to NOT use distributed ram, so it is very small in all vendors FPGA's it does have a compromise, 1 instruction takes 4 clock, but well then it has windowed register file and no overhead context switching, i do consider it much more interesting then ATOM, at least what goes soft cores for FPGA Antti
From: glen herrmannsfeldt on 6 Mar 2010 16:46 Antti <antti.lukats(a)googlemail.com> wrote: (snip) > 1) the 4-bit "Atom" isnt so new ;) > 2) NanoBlaze is registered trademark of Xilinx A quick search of uspto.gov didn't find nanoblaze, but, following the pattern, the 4 bit processor would be femtoblaze, which also doesn't seem to be registered. -- glen
From: -jg on 6 Mar 2010 19:09
On Mar 7, 10:06 am, Antti <antti.luk...(a)googlemail.com> wrote: > > Jim, > > 1) the 4-bit "Atom" isnt so new ;) It is, relative to an 80C51 ;) > hm... one of my softcores has been pushed into useable status > its small core that is optimized to run from one single block ram > and to NOT use distributed ram, so it is very small in all vendors > FPGA's > it does have a compromise, 1 instruction takes 4 clock, but well then > it has windowed register file and no overhead context switching, i do > consider > it much more interesting then ATOM, at least what goes soft cores for FPGA Yes, a core that targets BlockRam is going to be a better fit. Windowed register is too often overlooked. Single cycle opcodes are over-rated, and I like the XMOS approach, where they time-slice to give the illusion of 4 x 100MHz cores. In a serial Flash CPU, to avoid thrashing the serial memory, and give superfast interrupts, you would allocate a small, fast interrupt/FSM type area, and then have one thread allowed to access serial flash. Serial flash also naturally has a clocks/opcode number. One chip will feed 16b/4 clocks, 24b in 6 clocks, and a Pair, would give 32b in 4 clocks, 40b in 5 clocks. -jg |