FSM in BlockRAM
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From: de4 on 5 Mar 2010 06:39 Hello to all ! I've problem with finite state machine. Because I have not much place in my FPGA and I need to create few more FSM i found that FSM logic can be packed in to BRAM. I created simple FSM in VHDL and it shows in raport that it uses Bram but there is a warning : WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please check that the RAM contents is read synchronously. I tried to make the simplest FSM but it dont change anything... Can someone show me an example of code in VHDL of simple state machine that can be packed in to BRAM with any warnings, errors. I just worry that my design won't work. I have ISE 11.1 and Spartan 3a... Thanks for any response... XST log : Reading design: binary.prj ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/FPGA PRAM/Debug/MultiCore/Example.vhd" in Library work. Architecture behv of Entity binary is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity <binary> in library <work> (architecture <behv>). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity <binary> in library <work> (Architecture <behv>). Set property "ENUM_ENCODING = 001 010 011 100 101 110 111" for signal <CS>. Set property "ENUM_ENCODING = 001 010 011 100 101 110 111" for signal <NS>. Entity <binary> analyzed. Unit <binary> generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit <binary>. Related source file is "C:/FPGA PRAM/Debug/MultiCore/Example.vhd". Found finite state machine <FSM_0> for signal <CS>. ----------------------------------------------------------------------- | States | 7 | | Transitions | 16 | | Inputs | 6 | | Outputs | 3 | | Clock | CLOCK (rising_edge) | | Power Up State | s1 | | Encoding | compact | | Implementation | BRAM | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit <binary> synthesized. ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Implementing FSM <FSM_0> on signal <CS> on BRAM. Synthesizing (advanced) Unit <CS>. WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please check that the RAM contents is read synchronously. ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 512-word x 6-bit | | | mode | write-first | | | clkA | connected to signal <Clk_FSM> | rise | | weA | connected to internal node | high | | addrA | connected to signal <In0> | | | diA | connected to internal node | | | doA | connected to signal <Out2> | | ----------------------------------------------------------------------- | optimization | area | | ----------------------------------------------------------------------- Unit <CS> synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <binary> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block binary, actual ratio is 0. Final Macro Processing ... ========================================================================= Final Register Report Found no macro ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLOCK | BUFGP | 1 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -5 Minimum period: 2.625ns (Maximum Frequency: 380.952MHz) Minimum input arrival time before clock: 1.342ns Maximum output required time after clock: 6.860ns Maximum combinational path delay: No path found ========================================================================= Process "Synthesis" completed successfully --------------------------------------- Posted through http://www.FPGARelated.com
From: Symon on 5 Mar 2010 07:41 On 3/5/2010 11:39 AM, de4 wrote: > > Can someone show me an example of code in VHDL of simple state machine that > can be packed in to BRAM with any warnings, errors. I just worry that my > design won't work. I have ISE 11.1 and Spartan 3a... > XAPP291
From: Antti on 5 Mar 2010 11:08 On Mar 5, 2:41 pm, Symon <symon_bre...(a)hotmail.com> wrote: > On 3/5/2010 11:39 AM, de4 wrote: > > > > > Can someone show me an example of code in VHDL of simple state machine that > > can be packed in to BRAM with any warnings, errors. I just worry that my > > design won't work. I have ISE 11.1 and Spartan 3a... > > XAPP291 xapp291 does NOT show how from SM VHDL code a implementation using BRAM is generated by the tools Antti
From: Symon on 5 Mar 2010 11:14 On 3/5/2010 4:08 PM, Antti wrote: > On Mar 5, 2:41 pm, Symon<symon_bre...(a)hotmail.com> wrote: >> On 3/5/2010 11:39 AM, de4 wrote: >> >> >> >>> Can someone show me an example of code in VHDL of simple state machine that >>> can be packed in to BRAM with any warnings, errors. I just worry that my >>> design won't work. I have ISE 11.1 and Spartan 3a... >> >> XAPP291 > > xapp291 does NOT show how from SM VHDL code a implementation using > BRAM is generated by the tools > > Antti But it _IS_ an example of 'code in VHDL of [a] simple state machine that can be packed in to BRAM'. Syms.
From: Andy Peters on 5 Mar 2010 11:56
On Mar 5, 4:39 am, "de4" <de4(a)n_o_s_p_a_m.poczta.onet.pl> wrote: > Hello to all ! > > I've problem with finite state machine. Because I have not much place in my > FPGA and I need to create few more FSM i found that FSM logic can be packed > in to BRAM. I created simple FSM in VHDL and it shows in raport that it > uses Bram but there is a warning : > > WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please > check that the RAM contents is read synchronously. > > I tried to make the simplest FSM but it dont change anything... Are you using the two-process state machine construct? If so, DON'T. -a |