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From: jack.gassett on 23 Nov 2009 12:17
Hello,

We are working on a project to create a low cost Open Source Logic
Analyzer. We are making great progress but would greatly appreciate
any input from members of the comp.arch.fpga group.

The design is based on the following resources:
-Sump Logic Analyzer VHDL design. (http://www.sump.org/projects/
analyzer/)
-Butterfly Light Hardware implementation. The goal is to streamline
the Butterfly Light hardware to reduce costs. (http://
www.gadgetfactory.net/gf/project/lax/)

If you have some time please take a look and give us you thoughts
about the project. The design pages are:
http://www.gadgetfactory.net/gf/project/butterflylogic/

All discussions about the project are located at:
http://whereisian.com/forum/index.php?board=23.0

Thank you,
Jack.
From: Uwe Bonnes on 23 Nov 2009 16:51
jack.gassett <jack.gassett(a)gadgetfactory.net> wrote:
> Hello,

> We are working on a project to create a low cost Open Source Logic
> Analyzer. We are making great progress but would greatly appreciate
> any input from members of the comp.arch.fpga group.

> The design is based on the following resources:
> -Sump Logic Analyzer VHDL design. (http://www.sump.org/projects/
> analyzer/)
> -Butterfly Light Hardware implementation. The goal is to streamline
> the Butterfly Light hardware to reduce costs. (http://
> www.gadgetfactory.net/gf/project/lax/)

> If you have some time please take a look and give us you thoughts
> about the project. The design pages are:
> http://www.gadgetfactory.net/gf/project/butterflylogic/

> All discussions about the project are located at:
> http://whereisian.com/forum/index.php?board=23.0

Argh, registration required...
--
Uwe Bonnes bon(a)elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
From: emeb on 1 Dec 2009 12:08
On Nov 23, 10:17 am, "jack.gassett" <jack.gass...(a)gadgetfactory.net>
wrote:
> Hello,
>
> We are working on a project to create a low cost Open Source Logic
> Analyzer. We are making great progress but would greatly appreciate
> any input from members of the comp.arch.fpga group.
>
> The design is based on the following resources:
> -Sump Logic Analyzer VHDL design. (http://www.sump.org/projects/
> analyzer/)
> -Butterfly Light Hardware implementation. The goal is to streamline
> the Butterfly Light hardware to reduce costs. (http://www.gadgetfactory.net/gf/project/lax/)
>
> If you have some time please take a look and give us you thoughts
> about the project. The design pages are:http://www.gadgetfactory.net/gf/project/butterflylogic/
>
> All discussions about the project are located at:http://whereisian.com/forum/index.php?board=23.0
>
> Thank you,
> Jack.

Looks pretty nice. Simple little system is usable for many types of
designs and the price is fairly reasonable (cheaper dev-boards are
available from mfgs/distros with more features however). It's pretty
bare-bones though: no signal conditioning, no cables / connectors.
Very DIY.

I'd say that for cost reduction and ergonomics you'd want to do the
following at a minimum:
* combine the USB & power conditioning with the FPGA onto one small
board.
* Eliminate unused I/O
* Add input signal conditioning to prevent damage to FPGA from
external sources
* Add some sort of standard connectors for multi-bit cables.
* Consider a board profile that would fit in a standard enclosure.

Newer Spartan 3A parts in the VQ100 package are now available from the
usual suspects and are a few $$ cheaper than the S3E you're currently
using. I'm guessing you could get the whole thing in for under $60
BOM. At that price though I'm wondering how well it competes with low-
end USB logic analyzers that are already out there.

Eric

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