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From: maxascent on 23 Nov 2009 06:47
I am looking at using the ISERDES block in a V5 design for a DDR2
controller. I want to input the DQ into an IODELAY block and then into the
ISERDES. Problem is I am not sure that you can do this anymore. I have seen
some old app notes with this configuration and a DDLY input on the ISERDES.
But the new user guides dont have this input and they call the ISERDES a
NODELAY block. Does anyone know anymore info regarding this?

Jon

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From: maxascent on 23 Nov 2009 08:27
It looks like you can use the ISERDES with an IODELAY but you have to
instantiate a Virtex 4 ISERDES not the Virtex 5 ISEDES_NODELAY. Just tried
it with ISE and it mapped and p&r ok.

Jon

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From: Bob Sakamoto on 23 Nov 2009 20:20
On Nov 23, 6:47 am, "maxascent" <maxasc...(a)yahoo.co.uk> wrote:
> I am looking at using the ISERDES block in a V5 design for a DDR2
> controller. I want to input the DQ into an IODELAY block and then into the
> ISERDES. Problem is I am not sure that you can do this anymore. I have seen
> some old app notes with this configuration and a DDLY input on the ISERDES.
> But the new user guides dont have this input and they call the ISERDES a
> NODELAY block. Does anyone know anymore info regarding this?
>
> Jon        
>
> ---------------------------------------        
> This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com

There are some race conditions associated with DDR2 and ISERDES IIRC.
Wh dont you use the Memory Interface Generator (MIG) in coregen?
From: maxascent on 24 Nov 2009 03:56
What kind of race conditions?
MIG is ok but I would rather have my own so I can be sure what its doing.

Jon

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