I'd rather switch than fight!
in [FPGA]
|
From: rickman on 8 May 2010 23:26 Everything snipped... That is why I am going to take a good look at Verilog. I've been using VHDL for some 12 years and I still don't feel like I completely understand even basic things like how signed/unsigned relate to std_ulogic and how closely related types... well, relate! When you convert slv to unsigned or unsigned using unsigned(), this is not really a conversion is it? It is not the same as using to_integer() to convert signed to integer. In the std_numeric library they include conversion functions between integer and signed/ unsigned. But there are no functions to convert slv and these types. So it would seem this is not a conversion by function. So what is it? At one time I thought I understood all this, but it is so far removed from getting work done that I typically adopt standard practices and forget the details. Then when I need to figure out something new I have to go back to basics. It just gets so time consuming. I want to focus on the work, not the method. Rick
From: Pete Fraser on 8 May 2010 23:56 "rickman" <gnuarm(a)gmail.com> wrote in message news:34aaac95-f886-481d-a4bb-a6b9c63b336f(a)r11g2000yqa.googlegroups.com... > When you convert slv to unsigned or unsigned using unsigned(), this is > not really a conversion is it? It is not the same as using > to_integer() to convert signed to integer. In the std_numeric library > they include conversion functions between integer and signed/ > unsigned. But there are no functions to convert slv and these types. > So it would seem this is not a conversion by function. So what is > it? If you're not doing arithemetic on it, nobody cares, and slv is fine. If you're doing arithmetic (adding, subtracting, multiplying, comparing to integer, etc) it tells the synthesizer and / or simulator whether you consider the N bits to represent an unsigned number (0 to 2^N -1) or a two's complement signed number (-(2^(N-1)) to 2^(N-1) -1). Pete
From: KJ on 9 May 2010 18:09 On May 8, 11:26 pm, rickman <gnu...(a)gmail.com> wrote: > Everything snipped... > You're welcome > That is why I am going to take a good look at Verilog. Then go take a look > I've been > using VHDL for some 12 years and I still don't feel like I completely > understand even basic things like how signed/unsigned relate to > std_ulogic and how closely related types... well, relate! > It was in what the snipped part that you pitched out so ungloriously at the start...maybe you shouldn't be so hasty > When you convert slv to unsigned or unsigned using unsigned(), this is > not really a conversion is it? Yes, it converts a std_logic_vector to an unsigned type...if it makes you feel better think of it as applying a particular numeric interpretation to a collection of bits so that you can add them, subtract them > It is not the same as using > to_integer() to convert signed to integer. Perhaps you should explain why you think that 'to_integer' is somehow different than converting between std_logic_vectors and (un)signed? Hint: They're fundamentally not...they are both converting between things of different types. > In the std_numeric library > they include conversion functions between integer and signed/ > unsigned. But there are no functions to convert slv and these types. slv_sig <= std_logic_vector(uns_sig); un_sig1 <= unsigned(slv_sig); What's the trouble? > So it would seem this is not a conversion by function. It would seem you missed how to convert between the types...not that they are not type conversion functions. > So what is > it? A type conversion > > At one time I thought I understood all this, but it is so far removed > from getting work done that I typically adopt standard practices and > forget the details. Then when I need to figure out something new I > have to go back to basics. It just gets so time consuming. I want to > focus on the work, not the method. > Good luck with Verilog KJ
From: Andy on 10 May 2010 12:46 I thought there was a change in the latest version of vhdl that redefined std_logic_vector as a resolved subtype of std_ulogic_vector? That would make SLV and SULV as interchangeable as SL and SUL. Anyway, VHDL allows for "built-in" conversions (explicitly invoked) between "closely related" aggregate types. "CR" means that both types are aggregates of the same element type. These built-in conversions are invoked by simply using the name of the target type, so to convert SLV to unsigned, you just need "unsigned(my_slv)". BTW, I always create a subtype slv as follows: subtype slv is std_logic_vector; Now, "slv" is its own (sub)type name which can be used for declarations, and even a built-in conversion invocation: my_slv <= slv(my_unsigned); You could probably do the same thing with an alias, but I figured out the subtype trick first. Andy
From: Andy Peters on 11 May 2010 13:23
On May 8, 8:26 pm, rickman <gnu...(a)gmail.com> wrote: > Everything snipped... > > That is why I am going to take a good look at Verilog. I've been > using VHDL for some 12 years and I still don't feel like I completely > understand even basic things like how signed/unsigned relate to > std_ulogic and how closely related types... well, relate! Well, since Verilog knows nothing about types, there are no conversions. But you do a lot of DSP, and proper numeric representation is obviously important. You'll go absolutely batshit crazy trying to sort out numeric operations in Verilog. (And don't buy into that line about how "C and Verilog are highly similar.") FWIW, I tend to always use VHDL's unsigned() and signed() (as needed) types in preference to std_logic_vectors when the arrays of bits represent actual numbers. I also use unsigned() and signed() types on port lists. For things like counters, I use ranged naturals, unless of course the count can be negative. -a |