I'd rather switch than fight!
in [FPGA]
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From: Patrick Maupin on 11 May 2010 17:07 On May 11, 12:23 pm, Andy Peters <goo...(a)latke.net> wrote: > But you do a lot of DSP, and proper numeric representation is > obviously important. You'll go absolutely batshit crazy trying to sort > out numeric operations in Verilog. (And don't buy into that line about > how "C and Verilog are highly similar.") Verilog and DSP is not very difficult. And C is quite similar in some ways, although it does have nice features like structures that are not available in (non-System) Verilog. But, if you're happy coding with C, you can easily code most of your testbench in C with verilog. Regards, Pat
From: Robert Miles on 11 May 2010 22:45 "rickman" <gnuarm(a)gmail.com> wrote in message news:f7fe2df7-3398-4f24-8146-71192784abf7(a)t17g2000vbk.googlegroups.com... >I think I have about had it with VHDL. I've been using the > numeric_std library and eventually learned how to get around the > issues created by strong typing although it can be very arcane at > times. I have read about a few suggestions people are making to help > with some aspects of the language, like a selection operator like > Verilog has. But it just seems like I am always fighting some aspect > of the VHDL language. > > I guess part of my frustration is that I have yet to see where strong > typing has made a real difference in my work... at least an > improvement. My customer uses Verilog and has mentioned several times > how he had tried using VHDL and found it too arcane to bother with. > He works on a much more practical level than I often do and it seems > to work well for him. > > One of my goals over the summer is to teach myself Verilog so that I > can use it as well as I currently use VHDL. Then I can make a fully > informed decision about which I will continue to use. I'd appreciate > pointers on good references, web or printed. > > Without starting a major argument, anyone care to share their feelings > on the differences in the two languages? > > Rick The last time I searched the general-purpose jobs newsgroup for jobs available for either, there were about twice as many jobs available for VHDL as for Verilog. Looks to me like a good reason to learn both, and then stay current enough on both to be able to use either, as the job prefers. Robert Miles a Verilog user, retired early due to health reasons previously a LASAR 6 user and a Logic 5 user
From: rickman on 12 May 2010 00:20 On May 11, 10:45 pm, "Robert Miles" <mile...(a)usenet-news.net> wrote: > "rickman" <gnu...(a)gmail.com> wrote in message > > news:f7fe2df7-3398-4f24-8146-71192784abf7(a)t17g2000vbk.googlegroups.com... > > > > >I think I have about had it with VHDL. I've been using the > > numeric_std library and eventually learned how to get around the > > issues created by strong typing although it can be very arcane at > > times. I have read about a few suggestions people are making to help > > with some aspects of the language, like a selection operator like > > Verilog has. But it just seems like I am always fighting some aspect > > of the VHDL language. > > > I guess part of my frustration is that I have yet to see where strong > > typing has made a real difference in my work... at least an > > improvement. My customer uses Verilog and has mentioned several times > > how he had tried using VHDL and found it too arcane to bother with. > > He works on a much more practical level than I often do and it seems > > to work well for him. > > > One of my goals over the summer is to teach myself Verilog so that I > > can use it as well as I currently use VHDL. Then I can make a fully > > informed decision about which I will continue to use. I'd appreciate > > pointers on good references, web or printed. > > > Without starting a major argument, anyone care to share their feelings > > on the differences in the two languages? > > > Rick > > The last time I searched the general-purpose jobs newsgroup for jobs > available for either, there were about twice as many jobs available for > VHDL as for Verilog. Looks to me like a good reason to learn both, > and then stay current enough on both to be able to use either, as the > job prefers. Yes, I guess jobs is important to many, but I work for myself and my main customer uses Verilog. He hasn't had a problem with me using VHDL, but every time I express any exasperation with some aspect of VHDL I am reminded of how Verilog doesn't have that problem. I know of a few instances of when strong typing found bugs for me before they turned into lab bug searches... which is one of the main reasons for using such features. The earlier in the process bugs are found, the easier they are found and the smaller the impact. Still, there is a cost and the question is whether the cost is justified... Rick
From: Robert Miles on 12 May 2010 00:38 "rickman" <gnuarm(a)gmail.com> wrote in message news:95699341-d174-4ce0-89de-c169c903d86e(a)d39g2000yqa.googlegroups.com... On May 11, 10:45 pm, "Robert Miles" <mile...(a)usenet-news.net> wrote: > "rickman" <gnu...(a)gmail.com> wrote in message > > news:f7fe2df7-3398-4f24-8146-71192784abf7(a)t17g2000vbk.googlegroups.com... > > > > >I think I have about had it with VHDL. I've been using the > > numeric_std library and eventually learned how to get around the > > issues created by strong typing although it can be very arcane at > > times. I have read about a few suggestions people are making to help > > with some aspects of the language, like a selection operator like > > Verilog has. But it just seems like I am always fighting some aspect > > of the VHDL language. > > > I guess part of my frustration is that I have yet to see where strong > > typing has made a real difference in my work... at least an > > improvement. My customer uses Verilog and has mentioned several times > > how he had tried using VHDL and found it too arcane to bother with. > > He works on a much more practical level than I often do and it seems > > to work well for him. > > > One of my goals over the summer is to teach myself Verilog so that I > > can use it as well as I currently use VHDL. Then I can make a fully > > informed decision about which I will continue to use. I'd appreciate > > pointers on good references, web or printed. > > > Without starting a major argument, anyone care to share their feelings > > on the differences in the two languages? > > > Rick > > The last time I searched the general-purpose jobs newsgroup for jobs > available for either, there were about twice as many jobs available for > VHDL as for Verilog. Looks to me like a good reason to learn both, > and then stay current enough on both to be able to use either, as the > job prefers. Yes, I guess jobs is important to many, but I work for myself and my main customer uses Verilog. He hasn't had a problem with me using VHDL, but every time I express any exasperation with some aspect of VHDL I am reminded of how Verilog doesn't have that problem. I know of a few instances of when strong typing found bugs for me before they turned into lab bug searches... which is one of the main reasons for using such features. The earlier in the process bugs are found, the easier they are found and the smaller the impact. Still, there is a cost and the question is whether the cost is justified... Rick --- Looks like you've had better luck than I did at finding new jobs without moving to another state to be near the job location. But then my last job ended back in 2002, so things could easily have changed since then. Robert Miles
From: KJ on 12 May 2010 07:59
>> On Apr 9, 10:07 am, rickman <gnu...(a)gmail.com> wrote: > > > I guess part of my frustration is that I have yet to see where strong > > > typing has made a real difference in my work... at least an > > > improvement. > On May 12, 12:20 am, rickman <gnu...(a)gmail.com> wrote: > I know > of a few instances of when strong typing found bugs for me before they > turned into lab bug searches... which is one of the main reasons for > using such features. The earlier in the process bugs are found, the > easier they are found and the smaller the impact. It seems you've already (re)discovered actual examples where type checking can be useful > Still, there is a > cost and the question is whether the cost is justified... > Depends strongly on the cost of a bug. KJ |