I2C Master Start stop generation
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From: Vips on 18 Jul 2010 00:33 Hi All I am implementing an I2C slave and low level interface to interface it to EEPROM. I am using I2c Master for verifying this module . The I2C Master code is reused from some other module. He has implemented the I2C in a fashion that the PULL up and the Pull Down is to be provided from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some other control signals. It doesnot generate a start and stop condition inside i2c master block. I have seen the code it waits for the SDA to go from LOW to HIGH .My question is 1. in I2C master do we have to make a separate module in verilog ( the code is in verilog) to generate start and stop condition. or it is expected to have this functionality inside the I2C master controller. 2. How do I connect for verifying the slave and the Interface . The SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), SDA_OUT( master) to SDA_IN( slave) . The confusion is the start and stop generation /detection module as it is not inside the controller has to be connected from outside. Will the START gen module just send SCL and SDA to I2c Master for start operation and the the master will take from there. 3. In the initial state when it is reset under normal protocol situation the SCL is Z and the SDA is Z both pulled up . To start the operation for a start gen condition is there a separate module to do so .How normally in I2C master it is done( someone who has already done it. 4. I have gone througn the standard but got confused as how the first start and stop condition is generated and who will toggle the first SDA low to high. I have googled also and looked for some reference designs but it is not running well in sumulation to understand how the first start operation is gereated as the slave is IDLE and waiting for the start signal from the master. I would highly appreciate any suggestions on this issue. Thanks in advance Vipul
From: Ed McGettigan on 18 Jul 2010 22:31 On Jul 17, 9:33 pm, Vips <thevipulsi...(a)gmail.com> wrote: > Hi All > > I am implementing an I2C slave and low level interface to interface it > to EEPROM. I am using I2c Master for verifying this module . The I2C > Master code is reused from some other module. He has implemented the > I2C in a fashion that the PULL up and the Pull Down is to be provided > from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some > other control signals. It doesnot generate a start and stop condition > inside i2c master block. I have seen the code it waits for the SDA to > go from LOW to HIGH .My question is > > 1. in I2C master do we have to make a separate module in verilog ( the > code is in verilog) to generate start and stop condition. or it is > expected to have this functionality inside the I2C master > controller. > 2. How do I connect for verifying the slave and the Interface . The > SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is > connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to > the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), > SDA_OUT( master) to SDA_IN( slave) . The confusion is the start and > stop generation /detection module as it is not inside the controller > has to be connected from outside. Will the START gen module just send > SCL and SDA to I2c Master for start operation and the the master will > take from there. > 3. In the initial state when it is reset under normal protocol > situation the SCL is Z and the SDA is Z both pulled up . To start the > operation for a start gen condition is there a separate module to do > so .How normally in I2C master it is done( someone who has already > done it. > 4. I have gone througn the standard but got confused as how the first > start and stop condition is generated and who will toggle the first > SDA low to high. > > I have googled also and looked for some reference designs but it is > not running well in sumulation to understand how the first start > operation is gereated as the slave is IDLE and waiting for the start > signal from the master. > > I would highly appreciate any suggestions on this issue. > > Thanks in advance > > Vipul Since the I2C Master generates the START and STOP commands it is very unusual that this is not part of the I2C Master that you are using. The START and STOP are integral parts of the communication protocol and it isn't clear to me how you could add this in parallel to the Master. Your description of using SDA_IN, SDA_OUT, SCL_IN and SCL_OUT for connections between the Master and Slave is also very unusual. Both of these cores should simple have a SDA and SCL bi-directional port that are connected with a weak PULLUP. The likely cause is that the author intended for a user add the bi-dir IO buffer in the top level, but there should also be able a SDA_TRI and SCL_TRI ports as well to control the direction. Ed McGettigan -- Xilinx Inc. Ed
From: Vips on 19 Jul 2010 00:11 On Jul 19, 7:31 am, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: > On Jul 17, 9:33 pm, Vips <thevipulsi...(a)gmail.com> wrote: > > > > > > > Hi All > > > I am implementing an I2C slave and low level interface to interface it > > to EEPROM. I am using I2c Master for verifying this module . The I2C > > Master code is reused from some other module. He has implemented the > > I2C in a fashion that the PULL up and the Pull Down is to be provided > > from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some > > other control signals. It doesnot generate a start and stop condition > > inside i2c master block. I have seen the code it waits for the SDA to > > go from LOW to HIGH .My question is > > > 1. in I2C master do we have to make a separate module in verilog ( the > > code is in verilog) to generate start and stop condition. or it is > > expected to have this functionality inside the I2C master > > controller. > > 2. How do I connect for verifying the slave and the Interface . The > > SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is > > connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to > > the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), > > SDA_OUT( master) to SDA_IN( slave) . The confusion is the start and > > stop generation /detection module as it is not inside the controller > > has to be connected from outside. Will the START gen module just send > > SCL and SDA to I2c Master for start operation and the the master will > > take from there. > > 3. In the initial state when it is reset under normal protocol > > situation the SCL is Z and the SDA is Z both pulled up . To start the > > operation for a start gen condition is there a separate module to do > > so .How normally in I2C master it is done( someone who has already > > done it. > > 4. I have gone througn the standard but got confused as how the first > > start and stop condition is generated and who will toggle the first > > SDA low to high. > > > I have googled also and looked for some reference designs but it is > > not running well in sumulation to understand how the first start > > operation is gereated as the slave is IDLE and waiting for the start > > signal from the master. > > > I would highly appreciate any suggestions on this issue. > > > Thanks in advance > > > Vipul > > Since the I2C Master generates the START and STOP commands it is very > unusual that this is not part of the I2C Master that you are using. > The START and STOP are integral parts of the communication protocol > and it isn't clear to me how you could add this in parallel to the > Master. > > Your description of using SDA_IN, SDA_OUT, SCL_IN and SCL_OUT for > connections between the Master and Slave is also very unusual. Both > of these cores should simple have a SDA and SCL bi-directional port > that are connected with a weak PULLUP. The likely cause is that the > author intended for a user add the bi-dir IO buffer in the top level, > but there should also be able a SDA_TRI and SCL_TRI ports as well to > control the direction. > > Ed McGettigan > -- > Xilinx Inc. > > Ed- Hide quoted text - > > - Show quoted text - Thanks for the reply.. Let me add that the Master has SDA_IN( input) SDA_TRISTATE( output) this is a simple output with no tristate. SCL_IN (input) SCL_TRISTATE(OUTPUT). Now I am confused as How the first start will be generated as who will toggle the SDA_IN line which is the input to the master for the START generation while the SCK_IN is high ....
From: Muzaffer Kal on 19 Jul 2010 01:37 On Sun, 18 Jul 2010 21:11:18 -0700 (PDT), Vips <thevipulsinha(a)gmail.com> wrote: >Thanks for the reply.. Let me add that the Master has SDA_IN( input) >SDA_TRISTATE( output) this is a simple output with no tristate. SCL_IN >(input) SCL_TRISTATE(OUTPUT). Now I am confused as How the first start >will be generated as who will toggle the SDA_IN line which is the >input to the master for the START generation while the SCK_IN is >high .... Because I2C is an open-drain (open collector) interface it doesn't need to drive any of the outputs high ie high level generation is done by the external pullup. This can be accomplished with a push-pull IO by driving a strong zero and tri-state for one. So you need a regular tri-state IO and drive zero when tri-state is inactive and tri-state when it is active ie (assuming active high tri-state IOPAD): IOPAD master_sda(.IN(sda_in), .OUT(sda_tristate), .OE(sda_tristate), ..PAD(sda_wire)); -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
From: Ed McGettigan on 19 Jul 2010 12:23
On Jul 18, 9:11 pm, Vips <thevipulsi...(a)gmail.com> wrote: > On Jul 19, 7:31 am, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: > > > > > > > On Jul 17, 9:33 pm, Vips <thevipulsi...(a)gmail.com> wrote: > > > > Hi All > > > > I am implementing an I2C slave and low level interface to interface it > > > to EEPROM. I am using I2c Master for verifying this module . The I2C > > > Master code is reused from some other module. He has implemented the > > > I2C in a fashion that the PULL up and the Pull Down is to be provided > > > from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some > > > other control signals. It doesnot generate a start and stop condition > > > inside i2c master block. I have seen the code it waits for the SDA to > > > go from LOW to HIGH .My question is > > > > 1. in I2C master do we have to make a separate module in verilog ( the > > > code is in verilog) to generate start and stop condition. or it is > > > expected to have this functionality inside the I2C master > > > controller. > > > 2. How do I connect for verifying the slave and the Interface . The > > > SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is > > > connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to > > > the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), > > > SDA_OUT( master) to SDA_IN( slave) . The confusion is the start and > > > stop generation /detection module as it is not inside the controller > > > has to be connected from outside. Will the START gen module just send > > > SCL and SDA to I2c Master for start operation and the the master will > > > take from there. > > > 3. In the initial state when it is reset under normal protocol > > > situation the SCL is Z and the SDA is Z both pulled up . To start the > > > operation for a start gen condition is there a separate module to do > > > so .How normally in I2C master it is done( someone who has already > > > done it. > > > 4. I have gone througn the standard but got confused as how the first > > > start and stop condition is generated and who will toggle the first > > > SDA low to high. > > > > I have googled also and looked for some reference designs but it is > > > not running well in sumulation to understand how the first start > > > operation is gereated as the slave is IDLE and waiting for the start > > > signal from the master. > > > > I would highly appreciate any suggestions on this issue. > > > > Thanks in advance > > > > Vipul > > > Since the I2C Master generates the START and STOP commands it is very > > unusual that this is not part of the I2C Master that you are using. > > The START and STOP are integral parts of the communication protocol > > and it isn't clear to me how you could add this in parallel to the > > Master. > > > Your description of using SDA_IN, SDA_OUT, SCL_IN and SCL_OUT for > > connections between the Master and Slave is also very unusual. Both > > of these cores should simple have a SDA and SCL bi-directional port > > that are connected with a weak PULLUP. The likely cause is that the > > author intended for a user add the bi-dir IO buffer in the top level, > > but there should also be able a SDA_TRI and SCL_TRI ports as well to > > control the direction. > > > Ed McGettigan > > -- > > Xilinx Inc. > > > Ed- Hide quoted text - > > > - Show quoted text - > > Thanks for the reply.. Let me add that the Master has SDA_IN( input) > SDA_TRISTATE( output) this is a simple output with no tristate. SCL_IN > (input) SCL_TRISTATE(OUTPUT). Now I am confused as How the first start > will be generated as who will toggle the SDA_IN line which is the > input to the master for the START generation while the SCK_IN is > high ....- Hide quoted text - > > - Show quoted text - The I2C Master issues the START and STOP and these doesn't just happen at the beginning and end of an operation. If the operation includes register address in the slave device then there is a second START that is issued after the register address is written followed by the slave address and then either reading or writing of the slave data. I think that you need to go back to the place that you got the I2C Master from and ask them for help because either you are misunderstanding their documentation or they have created a design that won't work well if at all. Ed McGettigan -- Xilinx Inc. |