IP2IP_Addr in IPIF
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From: agou on 2 Feb 2006 19:29 Hi, group I generated a IPIC interface by the Create and Import Peripheral Wizard to access PLB_DDR blockon the PLB bus. I chose the DMA, user logic Master Support mode. And then try to develop my own logic based on the generated files. Here, I have one problem: To write to an address on PLB bus, I need to provide two addresses: IP2IP_Addr which stores the source data and IP2Bus_Addr to which writes the data. Do I need to instantiate a BRAM in the FPGA to provide the source address? What I am not clear is whether the BRAM is compatible the IPIC logic. Or do I have to instantiate another PLB_Bram and then hook it up to the PLB? Are there any other simple method? Thank you for the help. Roger
From: Nju Njoroge on 3 Feb 2006 06:38 Hello, Please refer to this thread: http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/4373c26ee4c38328/aebfcf5e6f06f52c?lnk=st&q=PLB+Master&rnum=1&hl=en#aebfcf5e6f06f52c (Google "PLB Master" in Googe Groups and this will be your first hit). Properly using the IP2IP_Addr in the IPIF is what allowed my master to work properly. Good luck, NN agou wrote: > Hi, group > > I generated a IPIC interface by the Create and Import Peripheral Wizard > > to access PLB_DDR blockon the PLB bus. > > I chose the DMA, user logic Master Support mode. And then try to > develop my own logic based on the generated files. Here, I have one > problem: > > To write to an address on PLB bus, I need to provide two addresses: > IP2IP_Addr which stores the source data and IP2Bus_Addr > to which writes the data. Do I need to instantiate a BRAM in the FPGA > to provide the source address? > > What I am not clear is whether the BRAM is compatible the IPIC logic. > Or do I have to instantiate another PLB_Bram and then hook it up to the > PLB? Are there any other simple method? > > Thank you for the help. > Roger
From: agou on 3 Feb 2006 15:57 Hi, Nju Thank you for the reply. I don't know whether your code in last thread derived from the user_logic.v generated by the Create and Import Peripheral Wizard. And I am currently reading this code. In this code, there is a port named IP2IP_Addr, and in your last thread, you first connected with the IP2Bus_Addr and then you revised it to your local target memory. What I am not clear is that how to instantiate the "local target memory" which is compatible to the IPIF? Should I instantiate a PLB_BRAM block? Besides the above, in the user_logic.v, there is a 16 bytes flattened registers(mst_reg(0:15) in the sample code) which are used for the control from the software side. Meanwhile, in the sample code, each of this address is assigned a specific address, e.g. IP2IP register is located at C_BASEADDR+0x104. And I saw another reference design in which software could read these register directly by the address. So I just wonder whether I could allocate some other registers in my hardware and specify the address myself. If it could be done, then for writing, I could just store my data in these registers first and then assign these registers' addresses to the IP2IP_Addr. But I don't find anything on how to specify the registers' addresses in the sample code. So now, could you tell me how did you do to use a "local target memory"? And do you know whether the second method would work or not? Thank you Roger Nju Njoroge wrote: > Hello, > > Please refer to this thread: > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/4373c26ee4c38328/aebfcf5e6f06f52c?lnk=st&q=PLB+Master&rnum=1&hl=en#aebfcf5e6f06f52c > > (Google "PLB Master" in Googe Groups and this will be your first hit). > > Properly using the IP2IP_Addr in the IPIF is what allowed my master to > work properly. > > Good luck, > > NN > > > agou wrote: > > Hi, group > > > > I generated a IPIC interface by the Create and Import Peripheral Wizard > > > > to access PLB_DDR blockon the PLB bus. > > > > I chose the DMA, user logic Master Support mode. And then try to > > develop my own logic based on the generated files. Here, I have one > > problem: > > > > To write to an address on PLB bus, I need to provide two addresses: > > IP2IP_Addr which stores the source data and IP2Bus_Addr > > to which writes the data. Do I need to instantiate a BRAM in the FPGA > > to provide the source address? > > > > What I am not clear is whether the BRAM is compatible the IPIC logic. > > Or do I have to instantiate another PLB_Bram and then hook it up to the > > PLB? Are there any other simple method? > > > > Thank you for the help. > > Roger
From: Nju Njoroge on 4 Feb 2006 12:45 Hi Roger, The docs do not explain too well what they mean by "local target memory". If you notice, the Master PLB IPIF comes with a slave attachment. Thus, the master IPIF is not a pure master. Contrast this with the PPC Master interfaces (Instr-PLB and Data-PLB) which are pure masters. Because of the slave attachment, the master-slave IPIF has an address range like any PLB slave: you set this address range in the MHS file instantiation. The key insight (which the docs do not explain) is that the IP2IPBus_Addr should always be set to some address within the addressable range of the slave attachment. Thus, if your user_logic has internal memory, the idea is that you use the IP2IPBus_Addr address range for this "local target memory". If your master pcore does not need to have any internal memory, you can hard code IP2IPBus_Addr to a static address within the slave attachment address range. This was the case for me (I was designing a PLB to PLB bridge, so my data came from one side of the bridge and I pushed it out to the other side). Another thing to note is that the slave attachment is also used for master transactions. Master Read: Issue read request, the read data returns through the slave attachment, appearing like a write-request to your "local target memory". (Imagine after you receive the return data, you have to write it to your "local target memory"). Master Write: 1st read from "local target memory" using slave attachment, then you can push the data on the IP2Bus data bus with the external target address.... If found this scheme confusing, especially since not much documentation real estate was dedicated to explaining it. NN agou wrote: > Hi, Nju > > Thank you for the reply. I don't know whether your code in last thread > derived from the user_logic.v generated by the Create and Import > Peripheral Wizard. And I am currently reading this code. > > In this code, there is a port named IP2IP_Addr, and in your last > thread, you first connected with the IP2Bus_Addr and then you revised > it to your local target memory. What I am not clear is that how to > instantiate the "local target memory" which is compatible to the IPIF? > Should I instantiate a PLB_BRAM block? > > Besides the above, in the user_logic.v, there is a 16 bytes flattened > registers(mst_reg(0:15) in the sample code) which are used for the > control from the software side. Meanwhile, in the sample code, each of > this address is assigned a specific address, e.g. IP2IP register is > located at C_BASEADDR+0x104. And I saw another reference design in > which software could read these register directly by the address. So I > just wonder whether I could allocate some other registers in my > hardware and specify the address myself. If it could be done, then for > writing, I could just store my data in these registers first and then > assign these registers' addresses to the IP2IP_Addr. But I don't find > anything on how to specify the registers' addresses in the sample code. > > So now, could you tell me how did you do to use a "local target > memory"? And do you know whether the second method would work or not? > > Thank you > Roger > > Nju Njoroge wrote: > > Hello, > > > > Please refer to this thread: > > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/4373c26ee4c38328/aebfcf5e6f06f52c?lnk=st&q=PLB+Master&rnum=1&hl=en#aebfcf5e6f06f52c > > > > (Google "PLB Master" in Googe Groups and this will be your first hit). > > > > Properly using the IP2IP_Addr in the IPIF is what allowed my master to > > work properly. > > > > Good luck, > > > > NN > > > > > > agou wrote: > > > Hi, group > > > > > > I generated a IPIC interface by the Create and Import Peripheral Wizard > > > > > > to access PLB_DDR blockon the PLB bus. > > > > > > I chose the DMA, user logic Master Support mode. And then try to > > > develop my own logic based on the generated files. Here, I have one > > > problem: > > > > > > To write to an address on PLB bus, I need to provide two addresses: > > > IP2IP_Addr which stores the source data and IP2Bus_Addr > > > to which writes the data. Do I need to instantiate a BRAM in the FPGA > > > to provide the source address? > > > > > > What I am not clear is whether the BRAM is compatible the IPIC logic. > > > Or do I have to instantiate another PLB_Bram and then hook it up to the > > > PLB? Are there any other simple method? > > > > > > Thank you for the help. > > > Roger
From: Mich on 24 Feb 2006 06:59
Hi I 'm also trying to use a master ip on the PLB bus and I also use the IPIF interface from the "Create Peripheral" wizard in EDK's XPS. Like you I have some troubels with writhing and reading (I want to write and read to/from a BRAM on the PLB-Bus) You say that the slave attachment is also used for the master trasaction. When I look at the timing diagram on pg 116 of the plb_ipif.pdf (http://www.xilinx.com/bvdocs/ipcenter/data_sheet/plb_ipif.pdf) it say that when you read you will get a Bus2IP_WrReq is this correct, because you want to read and not write. Is this correct? I have made a small FSM to test a single read and write (at the bottom of the message is my VHDL-code) I have a state (PrepareWr_State and PrepareRd_State) to make sure all the addresses are correct I have a state (ReqWr_State and ReqRd_State) for the request => IP2Bus_MstWrReq and IP2Bus_MstRdReq I have a state (AckWr_State and AckRd_State) for the ack that the IPIF can read/write from/to my ip => IP2Bus_WrAck and IP2Bus_RdAck I have a state (OkWr_State and OkRd_State) so I know everything went well But there must be something wrong because it doesn't work, when I want to write something, my FSM stays in the ReqWr_State, and when I want to read something it also doesn't do what it should do (or atleast what I think it should do) Can you help me please? Mich -- TRANSITION_STATE_LOGIC STATE_TRANSITION_LOGIC: process (ACTUAL_STATE, pushR, pushL, pushU, pushD, Bus2IP_MstLastAck, Bus2IP_WrReq, Bus2IP_RdReq) variable counter_Rd : integer range 0 to 15; variable counter_Wr : integer range 0 to 15; begin case ACTUAL_STATE is when idle => if (pushR = '0') then -- pushR is active low NEXT_STATE <= PrepareWr_State; counter_Wr := 10; elsif (pushL = '0') then -- pushL is actief laag NEXT_STATE <= PrepareRd_State; counter_Rd := 10; else NEXT_STATE <= idle; end if; when PrepareWr_State => if (counter_Wr = 0) then NEXT_STATE <= ReqWr_State; else NEXT_STATE <= PrepareWr_State; counter_Wr := counter_Wr - 1; end if; when ReqWr_State => if (Bus2IP_MstLastAck = '1') then NEXT_STATE <= AckWr_State; else NEXT_STATE <= ReqWr_State; end if; when AckWr_State => if (Bus2IP_MstLastAck = '1') then NEXT_STATE <= OkWr_State; else NEXT_STATE <= AckWr_State; end if; when OkWr_State => -- Writing is ok if (pushU = '0') then -- PusU is active Low NEXT_STATE <= idle; else NEXT_STATE <= OkWr_State; end if; when PrepareRd_State => if (counter_Rd = 0) then NEXT_STATE <= ReqRd_State; else NEXT_STATE <= PrepareRd_State; counter_Rd := counter_Rd - 1; end if; when ReqRd_State => if (Bus2IP_WrReq = '1') then NEXT_STATE <= AckRd_State; else NEXT_STATE <= ReqRd_State; end if; when AckRd_State => if (Bus2IP_MstLastAck = '1') then NEXT_STATE <= OkRd_State; else NEXT_STATE <= AckRd_State; end if; when OkRd_State => -- Reading is ok if (pushD = '0') then -- pushD is actief laag NEXT_STATE <= idle; else NEXT_STATE <= OkRd_State; end if; when others => NEXT_STATE <= idle; end case; end process STATE_TRANSITION_LOGIC; -- TRANSITION_STATE_LOGIC -- OUTPUT_LOGIC OUTPUT_LOGIC: process (ACTUAL_STATE) begin case ACTUAL_STATE is when idle => led <= "1110"; IP2Bus_Data(0 to 3) <= schakelaar; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '0'; when PrepareWr_State => led <= "0001"; IP2Bus_Data(0 to 3) <= D_out; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '0'; when ReqWr_State => led <= "0010"; IP2Bus_Data(0 to 3) <= D_out; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '1'; when AckWr_State => led <= "0011"; IP2Bus_Data(0 to 3) <= D_out; IP2Bus_RdAck <= '1'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '1'; when OkWr_State => led <= "0100"; IP2Bus_Data(0 to 3) <= schakelaar; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '0'; when PrepareRd_State => led <= "1000"; IP2Bus_Data(0 to 3) <= D_out; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '0'; when ReqRd_State => led <= "1001"; IP2Bus_Data(0 to 3) <= D_out; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '1'; IP2Bus_MstWrReq <= '0'; when AckRd_State => led <= "1010"; IP2Bus_Data(0 to 3) <= D_out; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '1'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '1'; IP2Bus_MstWrReq <= '0'; when OkRd_State => if (D_out = Bus2IP_Data(0 to 3)) then led <= "1011"; else led <= "1100"; end if; IP2Bus_Data(0 to 3) <= schakelaar; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "11111111"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '0'; when others => led <= "1111"; IP2Bus_Data(0 to 3) <= schakelaar; IP2Bus_RdAck <= '0'; IP2Bus_WrAck <= '0'; IP2Bus_Addr <= C_Memory_Addr; IP2Bus_MstBE <= "00000000"; IP2Bus_MstRdReq <= '0'; IP2Bus_MstWrReq <= '0'; end case; end process OUTPUT_LOGIC; -- OUTPUT_LOGIC |