Interesting TIA design
in [Design]
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From: krw on 29 Oct 2009 20:15 On Thu, 29 Oct 2009 16:35:24 -0700, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Thu, 29 Oct 2009 18:31:28 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: > >>On Thu, 29 Oct 2009 11:00:46 -0700, Joerg <invalid(a)invalid.invalid> >>wrote: >> >>>John Larkin wrote: >>>> On Wed, 28 Oct 2009 19:26:47 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: >>>> >>> >>>[...] >>> >>>>> Good explanation (though I think I would have used a disco strobe as >>>>> an example ;). Don't teach her about "delta cycles" until she has the >>>>> basics down. >>>> >>>> I won't, because I have no idea what a delta cycle is. >>>> >>> >>>It's a bicycle: >> >>>http://www.deltacycle.com/BeltDrive_Bike#at >> >>;-) >> >>It's really VHDL's way of keeping everything from happening at once, >>while letting it happen at the same time. ;-) > >Clock skew is nature's way... Except that clock skew doesn't happen at the same time (i.e. you can measure it).
From: Joerg on 30 Oct 2009 12:54 krw wrote: > On Thu, 29 Oct 2009 16:35:24 -0700, John Larkin > <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >> On Thu, 29 Oct 2009 18:31:28 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: >> >>> On Thu, 29 Oct 2009 11:00:46 -0700, Joerg <invalid(a)invalid.invalid> >>> wrote: >>> >>>> John Larkin wrote: >>>>> On Wed, 28 Oct 2009 19:26:47 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: >>>>> >>>> [...] >>>> >>>>>> Good explanation (though I think I would have used a disco strobe as >>>>>> an example ;). Don't teach her about "delta cycles" until she has the >>>>>> basics down. >>>>> I won't, because I have no idea what a delta cycle is. >>>>> >>>> It's a bicycle: >>>> http://www.deltacycle.com/BeltDrive_Bike#at >>> ;-) >>> >>> It's really VHDL's way of keeping everything from happening at once, >>> while letting it happen at the same time. ;-) >> Clock skew is nature's way... > > Except that clock skew doesn't happen at the same time (i.e. you can > measure it). And then they change the process on you, about six months into production ... -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
From: krw on 30 Oct 2009 20:03
On Fri, 30 Oct 2009 09:54:36 -0700, Joerg <invalid(a)invalid.invalid> wrote: >krw wrote: >> On Thu, 29 Oct 2009 16:35:24 -0700, John Larkin >> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>> On Thu, 29 Oct 2009 18:31:28 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: >>> >>>> On Thu, 29 Oct 2009 11:00:46 -0700, Joerg <invalid(a)invalid.invalid> >>>> wrote: >>>> >>>>> John Larkin wrote: >>>>>> On Wed, 28 Oct 2009 19:26:47 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: >>>>>> >>>>> [...] >>>>> >>>>>>> Good explanation (though I think I would have used a disco strobe as >>>>>>> an example ;). Don't teach her about "delta cycles" until she has the >>>>>>> basics down. >>>>>> I won't, because I have no idea what a delta cycle is. >>>>>> >>>>> It's a bicycle: >>>>> http://www.deltacycle.com/BeltDrive_Bike#at >>>> ;-) >>>> >>>> It's really VHDL's way of keeping everything from happening at once, >>>> while letting it happen at the same time. ;-) >>> Clock skew is nature's way... >> >> Except that clock skew doesn't happen at the same time (i.e. you can >> measure it). > > >And then they change the process on you, about six months into >production ... Clock skew cuts into Vmax so, at least FPGA manufacturers, don't make it worse. Lower skew doesn't matter. Fortunately, lower is the natural tendency too. ;-) |