Inverting bits
in [DSP]
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From: Jerry Avins on 4 Jan 2010 09:33 Avier wrote: > suppose if am having a clock frequency of 60 Mhz and i want to invert > every third bit that is inverting signal at 20Mhz . what could be the > best solution in terms of least number of storage bits . > > i think a counter can be used but how many storage bits we will count > it? > > any other solutions We (those at comp.dsp who responded) missed the mark. As the first responder, it falls to me to apologize. Before inverting, it is necessary to know which bits to invert. Either the bit clock must be given separately, or it must be reconstructed from the data. Clever ways to divide by three are a trivial part of the solution. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
From: glen herrmannsfeldt on 4 Jan 2010 10:48 Jerry Avins <jya(a)ieee.org> wrote: > Avier wrote: >> suppose if am having a clock frequency of 60 Mhz and i want to invert >> every third bit that is inverting signal at 20Mhz . what could be the >> best solution in terms of least number of storage bits . >> i think a counter can be used but how many storage bits we will count >> it? >> any other solutions > We (those at comp.dsp who responded) missed the mark. As the first > responder, it falls to me to apologize. Before inverting, it is > necessary to know which bits to invert. Either the bit clock must be > given separately, or it must be reconstructed from the data. Clever ways > to divide by three are a trivial part of the solution. I was assuming a global reset, or some other such signal, such that the counter started at the right point. The main requirement seems to be to minimize storage bits, though, not gates or transistors. I claim that a storage device with three stable states stores log2(3) bits, as previously described. Note that many systems have more stable states than are actually used, and those should count toward stored bits. It seems common for FPGA designs to generate one-hot state machines. While only N states are used, there are usually still 2**N stable states. (Adding the extra logic to remove those states is too expensive.) Still, it is nice for a state machine to be designed such that if it is in an undesired state that it get to a desired state in a reasonable number of clock cycles. I have an MM5311 based digital clock. If it powers up higher than 12:59:59 it will count to 32:59:59 before going to 1:00:00. If it powers up past 32:59:59 it will count to 39:59:59. -- glen
From: Jerry Avins on 4 Jan 2010 11:04
glen herrmannsfeldt wrote: > Jerry Avins <jya(a)ieee.org> wrote: >> Avier wrote: >>> suppose if am having a clock frequency of 60 Mhz and i want to invert >>> every third bit that is inverting signal at 20Mhz . what could be the >>> best solution in terms of least number of storage bits . > >>> i think a counter can be used but how many storage bits we will count >>> it? > >>> any other solutions > >> We (those at comp.dsp who responded) missed the mark. As the first >> responder, it falls to me to apologize. Before inverting, it is >> necessary to know which bits to invert. Either the bit clock must be >> given separately, or it must be reconstructed from the data. Clever ways >> to divide by three are a trivial part of the solution. > > I was assuming a global reset, or some other such signal, such that > the counter started at the right point. I was assuming a bit clock. The question as posed doesn't imply one. > The main requirement seems to be to minimize storage bits, > though, not gates or transistors. A PLL to generate the bit clock will probably need a divider. ... Jerry -- Engineering is the art of making what you want from things you can get. ����������������������������������������������������������������������� |