Is it time to stop research in Computer Architecture ?
|
From: Robert Myers on 25 Oct 2009 12:12 On Oct 25, 6:36 am, Mayan Moudgill <ma...(a)bestweb.net> wrote: > Robert Myers wrote: > > > even if, in some rare awkward instances, it might > > take a while. Something about large prime numbers. > > I'm kind of lost here; which large prime numbers are involved? If you're > talking loops with fractional II, then those might behave better on an > OoO processors. Terje? Poor Terje, to whom I really do owe an apology. I'm pretty sure this part of the conversation makes sense only in the context of a processor with a trace cache where (given my primitive understanding of the Pentium 4 trace cache) in some circumstances it will sometimes take a long time for the OoO scheduler to find a stable "optimal" schedule for a given loop iteration. You have kindly pointed out that there are other circumstances where there are important differences between OoO and software pipelining. It probably would have been best if the discussion had been more careful from the very beginning. Robert.
From: "Andy "Krazy" Glew" on 25 Oct 2009 13:59 Bernd Paysan wrote: > Del Cecchi wrote: >> You could use SOI, no bulk. :-) > > There still is a bulk, there is just no substrate, so the bulk is left > floating. The diodes I mentioned are sill there, supplying the bulk > when forward biased (this is the well-known effect of SOI to have > variable gate thresholds through charging and discharging the bulk below > the diodes threshold, unless you add in a real bulk contact like on > stock silicon wafers). > >> I don't get the point of the AC. Light bulbs and space heaters are AC >> powered and still disipate power. What did I miss? > > I can't tell you. Andy apparently doesn't care much about the physics > behind integrated circuits, his knowledge stops at the gate level. This > is completely ok for digital design, but I wonder why he makes that sort > of suggestions ;-). Och! Wounded I am, ad-hominem'ed. What did I ever do to you, Bernd? Have you been taking lessons from Nick? Anyway, to address Del's question: In present electronics, electrons flow from the power supply, across lots of wires, to the switching circuit, across the circuit, and then back to the power supply. (Or holes if you want to get pedantic, but if you get pedantic, that's a whole other story behind holes.) The idea behind charge recovery is that, instead of making this round trip, you accumulate the charge that has flowed from high to low - and then somehow find a way to do more work with it. Have it flow across the circuit, get stored for a while, and then have it flow back again. This flowing first one way, then back the other, is why I call it AC. Alternating current (directions). This is not that common a terminology, although as I explained in my original post I am not the only person to think of it this way. Bernd apparently thought that I was espousing having the power rails for the entire chip reverse polarity - swapping, e.g. (+1,-1) or (+1,0). This doesn't work, for reasons Bernd explained. However, what I am talking about - what I have picked up from researchers in this field - is to still have power and ground rails at (1.5V,0) - but to have signal rails that are at (+1.3,+0.7). Then signal rails periodically reverse, to (+0.7,+1.3). This is why, in my original post, I was careful to say `The devices will have to work within a range of changing voltages, say when "high" is between k=1/3 and k=1 Vmax=(Vmean+k*Vswing), and "low" is between k=1/3 and k=1 Vmin=(Vmean-k*Vswing).' Where signal rails at (+0.7,+1.3) range, with power rails at (+1.5,0), Vmean=1V, VSwing = 0.3V, Vmax=1.3V, Vmin=0.7V. Can this be made to work? I'm sure that Bernd will tell me an answer; and, if I am lucky, we may get an answer frm somebody with more knowledge than either I or Bernd have. I think you can keep the devices properly biased under such a scheme. But then again, this is not my specialty. Even if it can be made to work, is there any advantage to doing it? Only if the round trip costs are significant; i.e. only if there is significant impedance in the power and ground networks, outside of the actual switching circuit that does the computation. Can you store the charge usefully? To my naive way of thinking, that implies capacitors, probably a bank on chip. (It's interesting to think about why AC ultimately beat the DC systems that Edison initially deployed. I don't think power efficiency in the device was a big part; mainly it was the ability to transmit AC longer distances, with the ease of transformers to change voltage level. Dissipation in transmission was part of it. I don;t know if this has any relevance to electronics.) > I can't tell you. Andy apparently doesn't care much about the physics > behind integrated circuits, his knowledge stops at the gate level.This > is completely ok for digital design, but I wonder why he makes that > sort of suggestions ;-). Over the years I have learned that, if at a dead end, one must ask stupid questions and come up with blue sky ideas, questioning the implicit assumptions of the field, and/or starting from first principles. Apparently we are approaching such a dead end wrt circuits. I'm not *that* afraid to embarrass myself. My definition of a computer architect is the guy who is able to go in and call "Bullshit" on any specialist in the team who is sandbagging and/or reporting obstacles. I've simplified logic by 100x. Dave Papworth, my former boss on P6, once showed that the process technology guys were sandbagging by more than 30% - he asked me for my CRC Handbook of Chemistry and Physics, looked up the physical properties of aluminum, and went and banged heads together. > One interesting property of quantum mechanics is that for irreversible > logic, there's a minimum amount of energy that is necessary to make it > happen. Reversible logic does not have this drawback. Therefore, > people investigate into reversible logic, even though the actual > components to get that benefit are not in sigh (not even carbon nanotube > switches have these properties, even though they are much closer to the > physical limits for irreversible logic). Many people also forget that > quantum mechanics does not properly take changes in the system into > account, and that means that your reversible logic only works with the > predicted low power when the inputs are not changing any more - and this > is just the uninteresting case (the coherent one - changes in the system > lead to decoherence, and thereby to classical physics). I've been around long enough that I remember, during the ECL to CMOS transition, when some people said that one of the advantages of CMOS was that it might support reversible, adiabatic, or charge recovery logic. Apparently that did not pan out, eh? Apparently reversible, adiabatic, or charge recovery logic is always a few generations ahead of the present technology, on materials a few generations ahead of the silicon-hafnium-germanium whatever we are using now. I can't help but wonder if this is part of the problem: the search for the perfect, the lowest possible power, as opposed to what can be done now. === Anyway, this may be a moot point. IEEE Spectrum October 2000, p.40 has an article by Pushkar Apte & George Scalise at the SIA, mentioning graphene base BiSFET (Bilayer pseudo-Spin Field Effect Transistors) (not to be confused with BISFET, the BI-Stable FET). They say the BiSFET "needs only one-hundredth to one-thousandth the power of a standard MOSFET".
From: "Andy "Krazy" Glew" on 25 Oct 2009 14:11 Bill Todd wrote: > Gavin Scott wrote: >> "Andy \"Krazy\" Glew" <ag-news(a)patten-glew.net> wrote: >>> I am not aware of an Itanium shipped or proposed that had an "x86 >>> core on the side". >> >> I'm pretty certain that Merced had hard support for x86 and McKinley >> may well have as well. > > Hardware support for x86 on Itanic existed on Merced, McKinley, Madison, > and Madison II (the one with the 9 MB on-chip cache), finally > disappearing in 2006 with Montecito. Aarghh!!! Read what I said: I'm not aware of any Itanium shipped or proposed that had "an x86 core on the side". I am aware of Itania that had hardware support for x86. If you care enough, go look up the patents. --- Perhaps the problem is terminology: to me, and to people at Intel, "x86 on the side" means that you have an x86 core right next to the Itanium core, connected at the bus, or perhaps the L1 or L2 cache. We similarly used the term "TCOTS", Tiny Core On The Side", to refer to something like having a big x86 core, and a small x86 core for when in power saving modes. As opposed to just powering up the big core for, say, 1ms every second. If you have an x86 decoder generating Itanium VLIW instructions, using Itanium execution units, cache hierarchy, and TLBs, perhaps with a few widget instructions and/or execution units, then that is not an x86 on the side.
From: Bill Todd on 25 Oct 2009 14:47 Andy "Krazy" Glew wrote: > Bill Todd wrote: >> Gavin Scott wrote: >>> "Andy \"Krazy\" Glew" <ag-news(a)patten-glew.net> wrote: >>>> I am not aware of an Itanium shipped or proposed that had an "x86 >>>> core on the side". >>> >>> I'm pretty certain that Merced had hard support for x86 and McKinley >>> may well have as well. >> >> Hardware support for x86 on Itanic existed on Merced, McKinley, >> Madison, and Madison II (the one with the 9 MB on-chip cache), finally >> disappearing in 2006 with Montecito. > > Aarghh!!! Read what I said: I did. However, I was not responding to you but to the statement that Gavin made (which could be interpreted to suggest opposition to your statement above or simply as clarification of the bounds within which that statement was valid, if he was not certain whether you were denying the existence of any hardware support for x86 on Itanic). You will note that my own phrasing (like Gavin's) was fairly precise in this area: I did not presume to know Gavin's intent, but clarifying how long hardware support for x86 existed on Itanic seemed appropriate given his uncertainty about that point. - bill
From: Bernd Paysan on 25 Oct 2009 14:54
Robert Myers wrote: > Let's see. Quantum mechanics properly applied takes account of > everything in the whole universe, which is, so far as I know, quantum > mechanical and reversible in it's entirety. Nope. That's just wishful thinking from people who do QM. The concepts behind decoherence are partly understood, and some even quantified (e.g. the critical temperature corresponds to what has been called "thermal de-Broglie wavelength", which more or less describes the relation between random changes in the conductor and a "volume of coherence"), but overall, this is not part of QM. QM describes what happens within the volume of coherence, classical physic describes what happens outside. There is no accepted unified theory that gives a good reason for this boundary and works equally well on both sides of the coherence fence. Note that when the "observer" is actually a quantum mechanical object, it won't disturb the other parts of the system - it will be part of this reversible dance. > Thus, even though you can't do operations with *no* net cost in > energy, we can still build and operate devices that act as quantum > mechanical computers to an arbitrarily good approximation. No, we can't. The quantum computer people are struggling with the same thermal de-Broglie wavelength as the superconducting people. Just that in quantum computing, the wavelength also depends on how many bits your system has - but unfortunately, it goes exponentially with the number of bits. So you can either make it arbitrary slow for many bits, or reduce the number of bits to an almost useless amount, but not both at the same time. The people who work on these research projects are certainly more optimistic than I am, but maybe Andy is right, and I've taken some lessons from Nick ;-). -- Bernd Paysan "If you want it done right, you have to do it yourself" http://www.jwdt.com/~paysan/ |