Prev: LVPECL to PECL to LVPECL
Next: Antenna for cordless phone
From: miso on 17 May 2010 04:24
On May 16, 1:44 pm, a7yvm109gf...(a)netzero.com wrote:
> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote:
>
>
>
> > On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote:
>
> > > I'm not understanding a line in a datasheet. ST Micro LD291500
>
> > > This monkey here
>
> > >http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-...
>
> > > Datasheet:
>
> > >http://www.st.com/stonline/books/pdf/docs/9614.pdf
>
> > > I want a linear post regulator for a 6V output switcher to get me a 5V
> > > supply at 1A max output current.
>
> > > Factoring in all the worst case bla bla bla, I need the regulator to
> > > work with less than 1V dropout. Seems simple enough.
>
> > > But on page 10 they give the dropout spec:
>
> > > 0.7V max with 1.5A out (I'll never get to 1.5A)
>
> > > But note 2 says
>
> > > Dropout voltage is defined as the input-to-output differential when
> > > the output voltage drops to 99 % of its nominal value with VO + 1 V
> > > applied to VI.
>
> > > OK, if you're applying VO+1V to VI, that's a 1V droput, no?
>
> > > So what does this mean? Will the part supply me a nominal 5V output at
> > > 1A throughout temp and 5.9V at the input?
>
> > > What does dropout mean here? 0.7v max or 1V or what?
>
> > > I feel dumb asking this, I guess I shouldn't have eaten that Big Mac
> > > in London ten years ago.
>
> > That is one poorly written datasheet. The 99% figure is probably some
> > fudge factor to compensate for the finite gain of the error amplifier.
> > Generally in a LDO, you don't have a lot of loop gain since stability
> > is more important that a few mV of output voltage accuracy.
>
> > The part is a bit cheesy in the GBD department, but perhaps no worse
> > than most stuff on the market. In the dark ages, you just GBD's say a
> > pins capacitance, something where it probably isn't worth the cost to
> > measure in a lot of situations. This part has leakage currents that
> > are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to
> > be typicalls 75db but could be as poor as 45dB.
>
> > Having designed a few of this type of chip, I prefer a p-fet pass
> > device over the PNP since as you approach dropout, the PNP will bleed
> > current out of the base.
>
> > The nice thing about a p-fet pass device is if the part is designed
> > properly, the high frequency PSRR is determined by the CDG of the pass
> > device and the filter cap. You can get very low feedthrough with good
> > chips. With PNP pass, if you glitch close to dropout, the anti-
> > saturation circuit in the chip comes into play. Figure 11 shows the
> > classic saturation problem as you approach dropout with a bipolar pass
> > device.
>
> > If the goal is to get rid of switcher noise, I'd think twice about
> > this part, or at least carefully evaluate it on the bench over
> > temperature for it's high frequency PSRR. This part doesn't even show
> > a PSRR versus frequency graph.
>
> I know, I've found in the past a lot of LDOs somehow dip a lot in the
> PSRR near about popular switcher frequencies.
> That's why I usually add a LC filter before the LDO.
> But in this case I have height, space and cost constraints for this
> design.
> And the ST part is one of the few parts that will (apparently) give 1A
> output with less than 1V dropout.
> Lots of "ultra" low LDOs don't give 1A output.
> What a life.
> Thanks to all for replies.

TI has a few MOS-pass LDOs that can handle high current. I don't know
the product line off the top of my head, but I've used their LDOs
without issue. TI generally runs the PSRR v frequency to a MHz because
they know people do put these after switchers. (AKA living in the real
world).


From: Phil Hobbs on 17 May 2010 08:57
miso(a)sushi.com wrote:
> On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote:
>> a7yvm109gf...(a)netzero.com wrote:
>>> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote:
>>>> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote:
>>>>> I'm not understanding a line in a datasheet. ST Micro LD291500
>>>>> This monkey here
>>>>> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-...
>>>>> Datasheet:
>>>>> http://www.st.com/stonline/books/pdf/docs/9614.pdf
>>>>> I want a linear post regulator for a 6V output switcher to get me a 5V
>>>>> supply at 1A max output current.
>>>>> Factoring in all the worst case bla bla bla, I need the regulator to
>>>>> work with less than 1V dropout. Seems simple enough.
>>>>> But on page 10 they give the dropout spec:
>>>>> 0.7V max with 1.5A out (I'll never get to 1.5A)
>>>>> But note 2 says
>>>>> Dropout voltage is defined as the input-to-output differential when
>>>>> the output voltage drops to 99 % of its nominal value with VO + 1 V
>>>>> applied to VI.
>>>>> OK, if you're applying VO+1V to VI, that's a 1V droput, no?
>>>>> So what does this mean? Will the part supply me a nominal 5V output at
>>>>> 1A throughout temp and 5.9V at the input?
>>>>> What does dropout mean here? 0.7v max or 1V or what?
>>>>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac
>>>>> in London ten years ago.
>>>> That is one poorly written datasheet. The 99% figure is probably some
>>>> fudge factor to compensate for the finite gain of the error amplifier.
>>>> Generally in a LDO, you don't have a lot of loop gain since stability
>>>> is more important that a few mV of output voltage accuracy.
>>>> The part is a bit cheesy in the GBD department, but perhaps no worse
>>>> than most stuff on the market. In the dark ages, you just GBD's say a
>>>> pins capacitance, something where it probably isn't worth the cost to
>>>> measure in a lot of situations. This part has leakage currents that
>>>> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to
>>>> be typicalls 75db but could be as poor as 45dB.
>>>> Having designed a few of this type of chip, I prefer a p-fet pass
>>>> device over the PNP since as you approach dropout, the PNP will bleed
>>>> current out of the base.
>>>> The nice thing about a p-fet pass device is if the part is designed
>>>> properly, the high frequency PSRR is determined by the CDG of the pass
>>>> device and the filter cap. You can get very low feedthrough with good
>>>> chips. With PNP pass, if you glitch close to dropout, the anti-
>>>> saturation circuit in the chip comes into play. Figure 11 shows the
>>>> classic saturation problem as you approach dropout with a bipolar pass
>>>> device.
>>>> If the goal is to get rid of switcher noise, I'd think twice about
>>>> this part, or at least carefully evaluate it on the bench over
>>>> temperature for it's high frequency PSRR. This part doesn't even show
>>>> a PSRR versus frequency graph.
>>> I know, I've found in the past a lot of LDOs somehow dip a lot in the
>>> PSRR near about popular switcher frequencies.
>>> That's why I usually add a LC filter before the LDO.
>>> But in this case I have height, space and cost constraints for this
>>> design.
>>> And the ST part is one of the few parts that will (apparently) give 1A
>>> output with less than 1V dropout.
>> Take a look at table 3 before you do that with a DPAK or PPAK. With 6V
>> in and 5V out you'll be burning a watt and that gets really toasty,
>> really fast. Muy caliente.
>>
>>> Lots of "ultra" low LDOs don't give 1A output.
>>> What a life.
>>> Thanks to all for replies.
>> Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-)
>>
>> --
>> Regards, Joerg
>>
>> http://www.analogconsultants.com/
>>
>> "gmail" domain blocked because of excessive spam.
>> Use another domain or send PM.
>
> So what is your alternative to LDOs? Hopefully not roll your own.
>
> I think these MOS LDOs are pretty good. MOS is mushy, but it's a good
> kind of mush.


Rolling one'w own makes a lot of sense sometimes. For running really
sensitive stuff off switching regulators, I like to use two-pole
capacitance multipliers with really slow op amp feedback loops wrapped
round them. Gets rid of 50-500 kHz to the tune of 100 dB.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
From: George Herold on 17 May 2010 09:28
On May 17, 8:57 am, Phil Hobbs
<pcdhSpamMeSensel...(a)electrooptical.net> wrote:
> m...(a)sushi.com wrote:
> > On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote:
> >> a7yvm109gf...(a)netzero.com wrote:
> >>> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote:
> >>>> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote:
> >>>>> I'm not understanding a line in a datasheet. ST Micro LD291500
> >>>>> This monkey here
> >>>>>http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-...
> >>>>> Datasheet:
> >>>>>http://www.st.com/stonline/books/pdf/docs/9614.pdf
> >>>>> I want a linear post regulator for a 6V output switcher to get me a 5V
> >>>>> supply at 1A max output current.
> >>>>> Factoring in all the worst case bla bla bla, I need the regulator to
> >>>>> work with less than 1V dropout. Seems simple enough.
> >>>>> But on page 10 they give the dropout spec:
> >>>>> 0.7V max with 1.5A out (I'll never get to 1.5A)
> >>>>> But note 2 says
> >>>>> Dropout voltage is defined as the input-to-output differential when
> >>>>> the output voltage drops to 99 % of its nominal value with VO + 1 V
> >>>>> applied to VI.
> >>>>> OK, if you're applying VO+1V to VI, that's a 1V droput, no?
> >>>>> So what does this mean? Will the part supply me a nominal 5V output at
> >>>>> 1A throughout temp and 5.9V at the input?
> >>>>> What does dropout mean here? 0.7v max or 1V or what?
> >>>>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac
> >>>>> in London ten years ago.
> >>>> That is one poorly written datasheet. The 99% figure is probably some
> >>>> fudge factor to compensate for the finite gain of the error amplifier.
> >>>> Generally in a LDO, you don't have a lot of loop gain since stability
> >>>> is more important that a few mV of output voltage accuracy.
> >>>> The part is a bit cheesy in the GBD department, but perhaps no worse
> >>>> than most stuff on the market. In the dark ages, you just GBD's say a
> >>>> pins capacitance, something where it probably isn't worth the cost to
> >>>> measure in a lot of situations. This part has leakage currents that
> >>>> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to
> >>>> be typicalls 75db but could be as poor as 45dB.
> >>>> Having designed a few of this type of chip, I prefer a p-fet pass
> >>>> device over the PNP since as you approach dropout, the PNP will bleed
> >>>> current out of the base.
> >>>> The nice thing about a p-fet pass device is if the part is designed
> >>>> properly, the high frequency PSRR is determined by the CDG of the pass
> >>>> device and the filter cap. You can get very low feedthrough with good
> >>>> chips. With PNP pass, if you glitch close to dropout, the anti-
> >>>> saturation circuit in the chip comes into play. Figure 11 shows the
> >>>> classic saturation problem as you approach dropout with a bipolar pass
> >>>> device.
> >>>> If the goal is to get rid of switcher noise, I'd think twice about
> >>>> this part, or at least carefully evaluate it on the bench over
> >>>> temperature for it's high frequency PSRR. This part doesn't even show
> >>>> a PSRR versus frequency graph.
> >>> I know, I've found in the past a lot of LDOs somehow dip a lot in the
> >>> PSRR near about popular switcher frequencies.
> >>> That's why I usually add a LC filter before the LDO.
> >>> But in this case I have height, space and cost constraints for this
> >>> design.
> >>> And the ST part is one of the few parts that will (apparently) give 1A
> >>> output with less than 1V dropout.
> >> Take a look at table 3 before you do that with a DPAK or PPAK. With 6V
> >> in and 5V out you'll be burning a watt and that gets really toasty,
> >> really fast. Muy caliente.
>
> >>> Lots of "ultra" low LDOs don't give 1A output.
> >>> What a life.
> >>> Thanks to all for replies.
> >> Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-)
>
> >> --
> >> Regards, Joerg
>
> >>http://www.analogconsultants.com/
>
> >> "gmail" domain blocked because of excessive spam.
> >> Use another domain or send PM.
>
> > So what is your alternative to LDOs? Hopefully not roll your own.
>
> > I think these MOS LDOs are pretty good. MOS is mushy, but it's a good
> > kind of mush.
>
> Rolling one'w own makes a lot of sense sometimes.  For running really
> sensitive stuff off switching regulators, I like to use two-pole
> capacitance multipliers with really slow op amp feedback loops wrapped
> round them.  Gets rid of 50-500 kHz to the tune of 100 dB.
>
> Cheers
>
> Phil Hobbs
>
> --
> Dr Philip C D Hobbs
> Principal
> ElectroOptical Innovations
> 55 Orchard Rd
> Briarcliff Manor NY 10510
> 845-480-2058
> hobbs at electrooptical dot nethttp://electrooptical.net- Hide quoted text -
>
> - Show quoted text -

Oh I like that, the opamp takes care of the crappy "DC" performance of
the cap. multiplier I assume.

George H.
From: Joerg on 17 May 2010 09:35
miso(a)sushi.com wrote:
> On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote:
>> a7yvm109gf...(a)netzero.com wrote:
>>> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote:
>>>> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote:
>>>>> I'm not understanding a line in a datasheet. ST Micro LD291500
>>>>> This monkey here
>>>>> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-...
>>>>> Datasheet:
>>>>> http://www.st.com/stonline/books/pdf/docs/9614.pdf
>>>>> I want a linear post regulator for a 6V output switcher to get me a 5V
>>>>> supply at 1A max output current.
>>>>> Factoring in all the worst case bla bla bla, I need the regulator to
>>>>> work with less than 1V dropout. Seems simple enough.
>>>>> But on page 10 they give the dropout spec:
>>>>> 0.7V max with 1.5A out (I'll never get to 1.5A)
>>>>> But note 2 says
>>>>> Dropout voltage is defined as the input-to-output differential when
>>>>> the output voltage drops to 99 % of its nominal value with VO + 1 V
>>>>> applied to VI.
>>>>> OK, if you're applying VO+1V to VI, that's a 1V droput, no?
>>>>> So what does this mean? Will the part supply me a nominal 5V output at
>>>>> 1A throughout temp and 5.9V at the input?
>>>>> What does dropout mean here? 0.7v max or 1V or what?
>>>>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac
>>>>> in London ten years ago.
>>>> That is one poorly written datasheet. The 99% figure is probably some
>>>> fudge factor to compensate for the finite gain of the error amplifier.
>>>> Generally in a LDO, you don't have a lot of loop gain since stability
>>>> is more important that a few mV of output voltage accuracy.
>>>> The part is a bit cheesy in the GBD department, but perhaps no worse
>>>> than most stuff on the market. In the dark ages, you just GBD's say a
>>>> pins capacitance, something where it probably isn't worth the cost to
>>>> measure in a lot of situations. This part has leakage currents that
>>>> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to
>>>> be typicalls 75db but could be as poor as 45dB.
>>>> Having designed a few of this type of chip, I prefer a p-fet pass
>>>> device over the PNP since as you approach dropout, the PNP will bleed
>>>> current out of the base.
>>>> The nice thing about a p-fet pass device is if the part is designed
>>>> properly, the high frequency PSRR is determined by the CDG of the pass
>>>> device and the filter cap. You can get very low feedthrough with good
>>>> chips. With PNP pass, if you glitch close to dropout, the anti-
>>>> saturation circuit in the chip comes into play. Figure 11 shows the
>>>> classic saturation problem as you approach dropout with a bipolar pass
>>>> device.
>>>> If the goal is to get rid of switcher noise, I'd think twice about
>>>> this part, or at least carefully evaluate it on the bench over
>>>> temperature for it's high frequency PSRR. This part doesn't even show
>>>> a PSRR versus frequency graph.
>>> I know, I've found in the past a lot of LDOs somehow dip a lot in the
>>> PSRR near about popular switcher frequencies.
>>> That's why I usually add a LC filter before the LDO.
>>> But in this case I have height, space and cost constraints for this
>>> design.
>>> And the ST part is one of the few parts that will (apparently) give 1A
>>> output with less than 1V dropout.
>> Take a look at table 3 before you do that with a DPAK or PPAK. With 6V
>> in and 5V out you'll be burning a watt and that gets really toasty,
>> really fast. Muy caliente.
>>
>>> Lots of "ultra" low LDOs don't give 1A output.
>>> What a life.
>>> Thanks to all for replies.
>> Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-)
>>
>> --
>> Regards, Joerg
>>
>> http://www.analogconsultants.com/
>>
>> "gmail" domain blocked because of excessive spam.
>> Use another domain or send PM.
>
> So what is your alternative to LDOs? Hopefully not roll your own.
>

Yes, I have rolled my own. Less grief that way. But my usual alternative
is a switcher.


> I think these MOS LDOs are pretty good. MOS is mushy, but it's a good
> kind of mush.


First I'd want to see some guaranteed specs WRT stability. Not some
"typical" graph but hard min and max numbers in the columns.

--
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.
From: MooseFET on 17 May 2010 09:38
On May 17, 1:14 am, "m...(a)sushi.com" <m...(a)sushi.com> wrote:
> On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote:
>
>
>
> > a7yvm109gf...(a)netzero.com wrote:
> > > On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote:
> > >> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote:
>
> > >>> I'm not understanding a line in a datasheet. ST Micro LD291500
> > >>> This monkey here
> > >>>http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-...
> > >>> Datasheet:
> > >>>http://www.st.com/stonline/books/pdf/docs/9614.pdf
> > >>> I want a linear post regulator for a 6V output switcher to get me a 5V
> > >>> supply at 1A max output current.
> > >>> Factoring in all the worst case bla bla bla, I need the regulator to
> > >>> work with less than 1V dropout. Seems simple enough.
> > >>> But on page 10 they give the dropout spec:
> > >>> 0.7V max with 1.5A out (I'll never get to 1.5A)
> > >>> But note 2 says
> > >>> Dropout voltage is defined as the input-to-output differential when
> > >>> the output voltage drops to 99 % of its nominal value with VO + 1 V
> > >>> applied to VI.
> > >>> OK, if you're applying VO+1V to VI, that's a 1V droput, no?
> > >>> So what does this mean? Will the part supply me a nominal 5V output at
> > >>> 1A throughout temp and 5.9V at the input?
> > >>> What does dropout mean here? 0.7v max or 1V or what?
> > >>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac
> > >>> in London ten years ago.
> > >> That is one poorly written datasheet. The 99% figure is probably some
> > >> fudge factor to compensate for the finite gain of the error amplifier.
> > >> Generally in a LDO, you don't have a lot of loop gain since stability
> > >> is more important that a few mV of output voltage accuracy.
>
> > >> The part is a bit cheesy in the GBD department, but perhaps no worse
> > >> than most stuff on the market. In the dark ages, you just GBD's say a
> > >> pins capacitance, something where it probably isn't worth the cost to
> > >> measure in a lot of situations. This part has leakage currents that
> > >> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to
> > >> be typicalls 75db but could be as poor as 45dB.
>
> > >> Having designed a few of this type of chip, I prefer a p-fet pass
> > >> device over the PNP since as you approach dropout, the PNP will bleed
> > >> current out of the base.
>
> > >> The nice thing about a p-fet pass device is if the part is designed
> > >> properly, the high frequency PSRR is determined by the CDG of the pass
> > >> device and the filter cap. You can get very low feedthrough with good
> > >> chips. With PNP pass, if you glitch close to dropout, the anti-
> > >> saturation circuit in the chip comes into play. Figure 11 shows the
> > >> classic saturation problem as you approach dropout with a bipolar pass
> > >> device.
>
> > >> If the goal is to get rid of switcher noise, I'd think twice about
> > >> this part, or at least carefully evaluate it on the bench over
> > >> temperature for it's high frequency PSRR. This part doesn't even show
> > >> a PSRR versus frequency graph.
>
> > > I know, I've found in the past a lot of LDOs somehow dip a lot in the
> > > PSRR near about popular switcher frequencies.
> > > That's why I usually add a LC filter before the LDO.
> > > But in this case I have height, space and cost constraints for this
> > > design.
> > > And the ST part is one of the few parts that will (apparently) give 1A
> > > output with less than 1V dropout.
>
> > Take a look at table 3 before you do that with a DPAK or PPAK. With 6V
> > in and 5V out you'll be burning a watt and that gets really toasty,
> > really fast. Muy caliente.
>
> > > Lots of "ultra" low LDOs don't give 1A output.
> > > What a life.
> > > Thanks to all for replies.
>
> > Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-)
>
> > --
> > Regards, Joerg
>
> >http://www.analogconsultants.com/
>
> > "gmail" domain blocked because of excessive spam.
> > Use another domain or send PM.
>
> So what is your alternative to LDOs? Hopefully not roll your own.
>
> I think these MOS LDOs are pretty good. MOS is mushy, but it's a good
> kind of mush.

I have designed several "roll my own" LDOs for specific
tasks. Try to find one that can withstand a 35V drop or
is stable into large good capacitors and you will see good
reasons to do it.

They also often have very poor high frequency line noise
rejection or just stick their legs in the air if you let
some RF leak onto them.

If you are going to need a reference in the design, it
is often a good move to make it bootstrapped by making
it work the LDO. It makes the LDO just basically an
op-amp.
First  |  Prev  |  Next  |  Last
Pages: 1 2 3 4 5
Prev: LVPECL to PECL to LVPECL
Next: Antenna for cordless phone