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From: Phil Hobbs on 18 May 2010 03:37 John Larkin wrote: > On Mon, 17 May 2010 08:57:14 -0400, Phil Hobbs > <pcdhSpamMeSenseless(a)electrooptical.net> wrote: > >> miso(a)sushi.com wrote: >>> On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote: >>>> a7yvm109gf...(a)netzero.com wrote: >>>>> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote: >>>>>> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote: >>>>>>> I'm not understanding a line in a datasheet. ST Micro LD291500 >>>>>>> This monkey here >>>>>>> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-... >>>>>>> Datasheet: >>>>>>> http://www.st.com/stonline/books/pdf/docs/9614.pdf >>>>>>> I want a linear post regulator for a 6V output switcher to get me a 5V >>>>>>> supply at 1A max output current. >>>>>>> Factoring in all the worst case bla bla bla, I need the regulator to >>>>>>> work with less than 1V dropout. Seems simple enough. >>>>>>> But on page 10 they give the dropout spec: >>>>>>> 0.7V max with 1.5A out (I'll never get to 1.5A) >>>>>>> But note 2 says >>>>>>> Dropout voltage is defined as the input-to-output differential when >>>>>>> the output voltage drops to 99 % of its nominal value with VO + 1 V >>>>>>> applied to VI. >>>>>>> OK, if you're applying VO+1V to VI, that's a 1V droput, no? >>>>>>> So what does this mean? Will the part supply me a nominal 5V output at >>>>>>> 1A throughout temp and 5.9V at the input? >>>>>>> What does dropout mean here? 0.7v max or 1V or what? >>>>>>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac >>>>>>> in London ten years ago. >>>>>> That is one poorly written datasheet. The 99% figure is probably some >>>>>> fudge factor to compensate for the finite gain of the error amplifier. >>>>>> Generally in a LDO, you don't have a lot of loop gain since stability >>>>>> is more important that a few mV of output voltage accuracy. >>>>>> The part is a bit cheesy in the GBD department, but perhaps no worse >>>>>> than most stuff on the market. In the dark ages, you just GBD's say a >>>>>> pins capacitance, something where it probably isn't worth the cost to >>>>>> measure in a lot of situations. This part has leakage currents that >>>>>> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to >>>>>> be typicalls 75db but could be as poor as 45dB. >>>>>> Having designed a few of this type of chip, I prefer a p-fet pass >>>>>> device over the PNP since as you approach dropout, the PNP will bleed >>>>>> current out of the base. >>>>>> The nice thing about a p-fet pass device is if the part is designed >>>>>> properly, the high frequency PSRR is determined by the CDG of the pass >>>>>> device and the filter cap. You can get very low feedthrough with good >>>>>> chips. With PNP pass, if you glitch close to dropout, the anti- >>>>>> saturation circuit in the chip comes into play. Figure 11 shows the >>>>>> classic saturation problem as you approach dropout with a bipolar pass >>>>>> device. >>>>>> If the goal is to get rid of switcher noise, I'd think twice about >>>>>> this part, or at least carefully evaluate it on the bench over >>>>>> temperature for it's high frequency PSRR. This part doesn't even show >>>>>> a PSRR versus frequency graph. >>>>> I know, I've found in the past a lot of LDOs somehow dip a lot in the >>>>> PSRR near about popular switcher frequencies. >>>>> That's why I usually add a LC filter before the LDO. >>>>> But in this case I have height, space and cost constraints for this >>>>> design. >>>>> And the ST part is one of the few parts that will (apparently) give 1A >>>>> output with less than 1V dropout. >>>> Take a look at table 3 before you do that with a DPAK or PPAK. With 6V >>>> in and 5V out you'll be burning a watt and that gets really toasty, >>>> really fast. Muy caliente. >>>> >>>>> Lots of "ultra" low LDOs don't give 1A output. >>>>> What a life. >>>>> Thanks to all for replies. >>>> Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-) >>>> >>>> -- >>>> Regards, Joerg >>>> >>>> http://www.analogconsultants.com/ >>>> >>>> "gmail" domain blocked because of excessive spam. >>>> Use another domain or send PM. >>> So what is your alternative to LDOs? Hopefully not roll your own. >>> >>> I think these MOS LDOs are pretty good. MOS is mushy, but it's a good >>> kind of mush. >> >> Rolling one'w own makes a lot of sense sometimes. For running really >> sensitive stuff off switching regulators, I like to use two-pole >> capacitance multipliers with really slow op amp feedback loops wrapped >> round them. Gets rid of 50-500 kHz to the tune of 100 dB. >> >> Cheers >> >> Phil Hobbs > > The worst thing about that config - and I'm doing a couple right now - > is the poor transient load regulation. It's great for steady loads. > The ideal regulator would clean up a noisy bulk supply to nanovolt > levels and still be stiff at the output. > > John > Understood--at all signal frequencies you're stuck with the behaviour of a barefoot BJT follower. OTOH that isn't so bad for a lot of things, especially frond end amps for photodiodes and other sensors with a lot of capacitance to worry about. It sure helps the PSR of op amps! Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
From: MooseFET on 18 May 2010 09:08 On May 18, 12:32 am, Phil Hobbs <pcdhSpamMeSensel...(a)electrooptical.net> wrote: > MooseFET wrote: > > On May 17, 5:57 am, Phil Hobbs > > <pcdhSpamMeSensel...(a)electrooptical.net> wrote: > >> m...(a)sushi.com wrote: > >>> On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote: > >>>> a7yvm109gf...(a)netzero.com wrote: > >>>>> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote: > >>>>>> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote: > >>>>>>> I'm not understanding a line in a datasheet. ST Micro LD291500 > >>>>>>> This monkey here > >>>>>>>http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-... > >>>>>>> Datasheet: > >>>>>>>http://www.st.com/stonline/books/pdf/docs/9614.pdf > >>>>>>> I want a linear post regulator for a 6V output switcher to get me a 5V > >>>>>>> supply at 1A max output current. > >>>>>>> Factoring in all the worst case bla bla bla, I need the regulator to > >>>>>>> work with less than 1V dropout. Seems simple enough. > >>>>>>> But on page 10 they give the dropout spec: > >>>>>>> 0.7V max with 1.5A out (I'll never get to 1.5A) > >>>>>>> But note 2 says > >>>>>>> Dropout voltage is defined as the input-to-output differential when > >>>>>>> the output voltage drops to 99 % of its nominal value with VO + 1 V > >>>>>>> applied to VI. > >>>>>>> OK, if you're applying VO+1V to VI, that's a 1V droput, no? > >>>>>>> So what does this mean? Will the part supply me a nominal 5V output at > >>>>>>> 1A throughout temp and 5.9V at the input? > >>>>>>> What does dropout mean here? 0.7v max or 1V or what? > >>>>>>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac > >>>>>>> in London ten years ago. > >>>>>> That is one poorly written datasheet. The 99% figure is probably some > >>>>>> fudge factor to compensate for the finite gain of the error amplifier. > >>>>>> Generally in a LDO, you don't have a lot of loop gain since stability > >>>>>> is more important that a few mV of output voltage accuracy. > >>>>>> The part is a bit cheesy in the GBD department, but perhaps no worse > >>>>>> than most stuff on the market. In the dark ages, you just GBD's say a > >>>>>> pins capacitance, something where it probably isn't worth the cost to > >>>>>> measure in a lot of situations. This part has leakage currents that > >>>>>> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to > >>>>>> be typicalls 75db but could be as poor as 45dB. > >>>>>> Having designed a few of this type of chip, I prefer a p-fet pass > >>>>>> device over the PNP since as you approach dropout, the PNP will bleed > >>>>>> current out of the base. > >>>>>> The nice thing about a p-fet pass device is if the part is designed > >>>>>> properly, the high frequency PSRR is determined by the CDG of the pass > >>>>>> device and the filter cap. You can get very low feedthrough with good > >>>>>> chips. With PNP pass, if you glitch close to dropout, the anti- > >>>>>> saturation circuit in the chip comes into play. Figure 11 shows the > >>>>>> classic saturation problem as you approach dropout with a bipolar pass > >>>>>> device. > >>>>>> If the goal is to get rid of switcher noise, I'd think twice about > >>>>>> this part, or at least carefully evaluate it on the bench over > >>>>>> temperature for it's high frequency PSRR. This part doesn't even show > >>>>>> a PSRR versus frequency graph. > >>>>> I know, I've found in the past a lot of LDOs somehow dip a lot in the > >>>>> PSRR near about popular switcher frequencies. > >>>>> That's why I usually add a LC filter before the LDO. > >>>>> But in this case I have height, space and cost constraints for this > >>>>> design. > >>>>> And the ST part is one of the few parts that will (apparently) give 1A > >>>>> output with less than 1V dropout. > >>>> Take a look at table 3 before you do that with a DPAK or PPAK. With 6V > >>>> in and 5V out you'll be burning a watt and that gets really toasty, > >>>> really fast. Muy caliente. > >>>>> Lots of "ultra" low LDOs don't give 1A output. > >>>>> What a life. > >>>>> Thanks to all for replies. > >>>> Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-) > >>>> -- > >>>> Regards, Joerg > >>>>http://www.analogconsultants.com/ > >>>> "gmail" domain blocked because of excessive spam. > >>>> Use another domain or send PM. > >>> So what is your alternative to LDOs? Hopefully not roll your own. > >>> I think these MOS LDOs are pretty good. MOS is mushy, but it's a good > >>> kind of mush. > >> Rolling one'w own makes a lot of sense sometimes. For running really > >> sensitive stuff off switching regulators, I like to use two-pole > >> capacitance multipliers with really slow op amp feedback loops wrapped > >> round them. Gets rid of 50-500 kHz to the tune of 100 dB. > > > I assume it is something like what I did: > > > Switcher ---[B]-------+--------+--[C]--GND > > ! ! > > [R] ! > > ! ! > > ! !/e > > +V1 +------! PNP > > ! NPN ! !\ > > Ref---!+\ !/ ! > > ! >---+--[R] --! ! > > --!-/ ! !\e ! > > ! ! ! ! > > +--[C]---- ----[R]-+--+--Load > > ! ! > > +------[R]----------------------- > > ! > > [R] > > ! > > GND > > > The bead and capacitor in the switcher path > > is just to remove the stuff up in the many MHz > > band. > > > The emitter resistor on the NPN is a very low > > value. 5 Ohms seems to work ok. It just keeps > > the gm of the output section from changing too > > much over the range of loads. If you use a > > buried zener reference, you can keep the noise > > on the supply down around 200nV/sqrt(Hz) so the > > amplifiers PSRR can easily do the rest. > > Nope, you use two cascaded RC lowpasses in the base lead. It has a > total of three lags in the loop...you have to make the op amp really > slow to avoid oscillation. You win by a factor of C_CE/C_bypass, which > can easily be 10**7. I see. My version of the circuit requires that the reference be quiet. Yours doesn't. > > Cheers > > Phil Hobbs > > -- > Dr Philip C D Hobbs > Principal > ElectroOptical Innovations > 55 Orchard Rd > Briarcliff Manor NY 10510 > 845-480-2058 > hobbs at electrooptical dot nethttp://electrooptical.net
From: Phil Hobbs on 19 May 2010 12:07 MooseFET wrote: > On May 18, 12:32 am, Phil Hobbs > <pcdhSpamMeSensel...(a)electrooptical.net> wrote: >> MooseFET wrote: >>> On May 17, 5:57 am, Phil Hobbs >>> <pcdhSpamMeSensel...(a)electrooptical.net> wrote: >>>> m...(a)sushi.com wrote: >>>>> On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote: >>>>>> a7yvm109gf...(a)netzero.com wrote: >>>>>>> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote: >>>>>>>> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote: >>>>>>>>> I'm not understanding a line in a datasheet. ST Micro LD291500 >>>>>>>>> This monkey here >>>>>>>>> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-... >>>>>>>>> Datasheet: >>>>>>>>> http://www.st.com/stonline/books/pdf/docs/9614.pdf >>>>>>>>> I want a linear post regulator for a 6V output switcher to get me a 5V >>>>>>>>> supply at 1A max output current. >>>>>>>>> Factoring in all the worst case bla bla bla, I need the regulator to >>>>>>>>> work with less than 1V dropout. Seems simple enough. >>>>>>>>> But on page 10 they give the dropout spec: >>>>>>>>> 0.7V max with 1.5A out (I'll never get to 1.5A) >>>>>>>>> But note 2 says >>>>>>>>> Dropout voltage is defined as the input-to-output differential when >>>>>>>>> the output voltage drops to 99 % of its nominal value with VO + 1 V >>>>>>>>> applied to VI. >>>>>>>>> OK, if you're applying VO+1V to VI, that's a 1V droput, no? >>>>>>>>> So what does this mean? Will the part supply me a nominal 5V output at >>>>>>>>> 1A throughout temp and 5.9V at the input? >>>>>>>>> What does dropout mean here? 0.7v max or 1V or what? >>>>>>>>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac >>>>>>>>> in London ten years ago. >>>>>>>> That is one poorly written datasheet. The 99% figure is probably some >>>>>>>> fudge factor to compensate for the finite gain of the error amplifier. >>>>>>>> Generally in a LDO, you don't have a lot of loop gain since stability >>>>>>>> is more important that a few mV of output voltage accuracy. >>>>>>>> The part is a bit cheesy in the GBD department, but perhaps no worse >>>>>>>> than most stuff on the market. In the dark ages, you just GBD's say a >>>>>>>> pins capacitance, something where it probably isn't worth the cost to >>>>>>>> measure in a lot of situations. This part has leakage currents that >>>>>>>> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to >>>>>>>> be typicalls 75db but could be as poor as 45dB. >>>>>>>> Having designed a few of this type of chip, I prefer a p-fet pass >>>>>>>> device over the PNP since as you approach dropout, the PNP will bleed >>>>>>>> current out of the base. >>>>>>>> The nice thing about a p-fet pass device is if the part is designed >>>>>>>> properly, the high frequency PSRR is determined by the CDG of the pass >>>>>>>> device and the filter cap. You can get very low feedthrough with good >>>>>>>> chips. With PNP pass, if you glitch close to dropout, the anti- >>>>>>>> saturation circuit in the chip comes into play. Figure 11 shows the >>>>>>>> classic saturation problem as you approach dropout with a bipolar pass >>>>>>>> device. >>>>>>>> If the goal is to get rid of switcher noise, I'd think twice about >>>>>>>> this part, or at least carefully evaluate it on the bench over >>>>>>>> temperature for it's high frequency PSRR. This part doesn't even show >>>>>>>> a PSRR versus frequency graph. >>>>>>> I know, I've found in the past a lot of LDOs somehow dip a lot in the >>>>>>> PSRR near about popular switcher frequencies. >>>>>>> That's why I usually add a LC filter before the LDO. >>>>>>> But in this case I have height, space and cost constraints for this >>>>>>> design. >>>>>>> And the ST part is one of the few parts that will (apparently) give 1A >>>>>>> output with less than 1V dropout. >>>>>> Take a look at table 3 before you do that with a DPAK or PPAK. With 6V >>>>>> in and 5V out you'll be burning a watt and that gets really toasty, >>>>>> really fast. Muy caliente. >>>>>>> Lots of "ultra" low LDOs don't give 1A output. >>>>>>> What a life. >>>>>>> Thanks to all for replies. >>>>>> Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-) >>>>>> -- >>>>>> Regards, Joerg >>>>>> http://www.analogconsultants.com/ >>>>>> "gmail" domain blocked because of excessive spam. >>>>>> Use another domain or send PM. >>>>> So what is your alternative to LDOs? Hopefully not roll your own. >>>>> I think these MOS LDOs are pretty good. MOS is mushy, but it's a good >>>>> kind of mush. >>>> Rolling one'w own makes a lot of sense sometimes. For running really >>>> sensitive stuff off switching regulators, I like to use two-pole >>>> capacitance multipliers with really slow op amp feedback loops wrapped >>>> round them. Gets rid of 50-500 kHz to the tune of 100 dB. >>> I assume it is something like what I did: >>> Switcher ---[B]-------+--------+--[C]--GND >>> ! ! >>> [R] ! >>> ! ! >>> ! !/e >>> +V1 +------! PNP >>> ! NPN ! !\ >>> Ref---!+\ !/ ! >>> ! >---+--[R] --! ! >>> --!-/ ! !\e ! >>> ! ! ! ! >>> +--[C]---- ----[R]-+--+--Load >>> ! ! >>> +------[R]----------------------- >>> ! >>> [R] >>> ! >>> GND >>> The bead and capacitor in the switcher path >>> is just to remove the stuff up in the many MHz >>> band. >>> The emitter resistor on the NPN is a very low >>> value. 5 Ohms seems to work ok. It just keeps >>> the gm of the output section from changing too >>> much over the range of loads. If you use a >>> buried zener reference, you can keep the noise >>> on the supply down around 200nV/sqrt(Hz) so the >>> amplifiers PSRR can easily do the rest. >> Nope, you use two cascaded RC lowpasses in the base lead. It has a >> total of three lags in the loop...you have to make the op amp really >> slow to avoid oscillation. You win by a factor of C_CE/C_bypass, which >> can easily be 10**7. > > I see. My version of the circuit requires that the reference be > quiet. > Yours doesn't. Yup--voltage references are horribly noisy--even worse than 300 kelvin resistors. You can get nanovolt noise at frequencies where you care about it, for things like photodiode biasing and discrete circuitry with poor supply rejection. Cheers Phil Hobbs
From: MooseFET on 19 May 2010 20:20
On May 19, 9:07 am, Phil Hobbs <pcdhSpamMeSensel...(a)electrooptical.net> wrote: > MooseFET wrote: > > On May 18, 12:32 am, Phil Hobbs > > <pcdhSpamMeSensel...(a)electrooptical.net> wrote: > >> MooseFET wrote: > >>> On May 17, 5:57 am, Phil Hobbs > >>> <pcdhSpamMeSensel...(a)electrooptical.net> wrote: > >>>> m...(a)sushi.com wrote: > >>>>> On May 16, 2:11 pm, Joerg <inva...(a)invalid.invalid> wrote: > >>>>>> a7yvm109gf...(a)netzero.com wrote: > >>>>>>> On May 16, 12:50 pm, "m...(a)sushi.com" <m...(a)sushi.com> wrote: > >>>>>>>> On May 16, 7:42 am, a7yvm109gf...(a)netzero.com wrote: > >>>>>>>>> I'm not understanding a line in a datasheet. ST Micro LD291500 > >>>>>>>>> This monkey here > >>>>>>>>>http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=497-... > >>>>>>>>> Datasheet: > >>>>>>>>>http://www.st.com/stonline/books/pdf/docs/9614.pdf > >>>>>>>>> I want a linear post regulator for a 6V output switcher to get me a 5V > >>>>>>>>> supply at 1A max output current. > >>>>>>>>> Factoring in all the worst case bla bla bla, I need the regulator to > >>>>>>>>> work with less than 1V dropout. Seems simple enough. > >>>>>>>>> But on page 10 they give the dropout spec: > >>>>>>>>> 0.7V max with 1.5A out (I'll never get to 1.5A) > >>>>>>>>> But note 2 says > >>>>>>>>> Dropout voltage is defined as the input-to-output differential when > >>>>>>>>> the output voltage drops to 99 % of its nominal value with VO + 1 V > >>>>>>>>> applied to VI. > >>>>>>>>> OK, if you're applying VO+1V to VI, that's a 1V droput, no? > >>>>>>>>> So what does this mean? Will the part supply me a nominal 5V output at > >>>>>>>>> 1A throughout temp and 5.9V at the input? > >>>>>>>>> What does dropout mean here? 0.7v max or 1V or what? > >>>>>>>>> I feel dumb asking this, I guess I shouldn't have eaten that Big Mac > >>>>>>>>> in London ten years ago. > >>>>>>>> That is one poorly written datasheet. The 99% figure is probably some > >>>>>>>> fudge factor to compensate for the finite gain of the error amplifier. > >>>>>>>> Generally in a LDO, you don't have a lot of loop gain since stability > >>>>>>>> is more important that a few mV of output voltage accuracy. > >>>>>>>> The part is a bit cheesy in the GBD department, but perhaps no worse > >>>>>>>> than most stuff on the market. In the dark ages, you just GBD's say a > >>>>>>>> pins capacitance, something where it probably isn't worth the cost to > >>>>>>>> measure in a lot of situations. This part has leakage currents that > >>>>>>>> are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to > >>>>>>>> be typicalls 75db but could be as poor as 45dB. > >>>>>>>> Having designed a few of this type of chip, I prefer a p-fet pass > >>>>>>>> device over the PNP since as you approach dropout, the PNP will bleed > >>>>>>>> current out of the base. > >>>>>>>> The nice thing about a p-fet pass device is if the part is designed > >>>>>>>> properly, the high frequency PSRR is determined by the CDG of the pass > >>>>>>>> device and the filter cap. You can get very low feedthrough with good > >>>>>>>> chips. With PNP pass, if you glitch close to dropout, the anti- > >>>>>>>> saturation circuit in the chip comes into play. Figure 11 shows the > >>>>>>>> classic saturation problem as you approach dropout with a bipolar pass > >>>>>>>> device. > >>>>>>>> If the goal is to get rid of switcher noise, I'd think twice about > >>>>>>>> this part, or at least carefully evaluate it on the bench over > >>>>>>>> temperature for it's high frequency PSRR. This part doesn't even show > >>>>>>>> a PSRR versus frequency graph. > >>>>>>> I know, I've found in the past a lot of LDOs somehow dip a lot in the > >>>>>>> PSRR near about popular switcher frequencies. > >>>>>>> That's why I usually add a LC filter before the LDO. > >>>>>>> But in this case I have height, space and cost constraints for this > >>>>>>> design. > >>>>>>> And the ST part is one of the few parts that will (apparently) give 1A > >>>>>>> output with less than 1V dropout. > >>>>>> Take a look at table 3 before you do that with a DPAK or PPAK. With 6V > >>>>>> in and 5V out you'll be burning a watt and that gets really toasty, > >>>>>> really fast. Muy caliente. > >>>>>>> Lots of "ultra" low LDOs don't give 1A output. > >>>>>>> What a life. > >>>>>>> Thanks to all for replies. > >>>>>> Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-) > >>>>>> -- > >>>>>> Regards, Joerg > >>>>>>http://www.analogconsultants.com/ > >>>>>> "gmail" domain blocked because of excessive spam. > >>>>>> Use another domain or send PM. > >>>>> So what is your alternative to LDOs? Hopefully not roll your own. > >>>>> I think these MOS LDOs are pretty good. MOS is mushy, but it's a good > >>>>> kind of mush. > >>>> Rolling one'w own makes a lot of sense sometimes. For running really > >>>> sensitive stuff off switching regulators, I like to use two-pole > >>>> capacitance multipliers with really slow op amp feedback loops wrapped > >>>> round them. Gets rid of 50-500 kHz to the tune of 100 dB. > >>> I assume it is something like what I did: > >>> Switcher ---[B]-------+--------+--[C]--GND > >>> ! ! > >>> [R] ! > >>> ! ! > >>> ! !/e > >>> +V1 +------! PNP > >>> ! NPN ! !\ > >>> Ref---!+\ !/ ! > >>> ! >---+--[R] --! ! > >>> --!-/ ! !\e ! > >>> ! ! ! ! > >>> +--[C]---- ----[R]-+--+--Load > >>> ! ! > >>> +------[R]----------------------- > >>> ! > >>> [R] > >>> ! > >>> GND > >>> The bead and capacitor in the switcher path > >>> is just to remove the stuff up in the many MHz > >>> band. > >>> The emitter resistor on the NPN is a very low > >>> value. 5 Ohms seems to work ok. It just keeps > >>> the gm of the output section from changing too > >>> much over the range of loads. If you use a > >>> buried zener reference, you can keep the noise > >>> on the supply down around 200nV/sqrt(Hz) so the > >>> amplifiers PSRR can easily do the rest. > >> Nope, you use two cascaded RC lowpasses in the base lead. It has a > >> total of three lags in the loop...you have to make the op amp really > >> slow to avoid oscillation. You win by a factor of C_CE/C_bypass, which > >> can easily be 10**7. > > > I see. My version of the circuit requires that the reference be > > quiet. > > Yours doesn't. > > Yup--voltage references are horribly noisy--even worse than 300 kelvin > resistors. You can get nanovolt noise at frequencies where you care > about it, for things like photodiode biasing and discrete circuitry with > poor supply rejection. Band gaps are really bad. 1.xxV with 500nV/sqrt(Hz) is a lot worse than 6.xxV with 100nV/sqrt(Hz) |