Memory in VHDL
in [FPGA]
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From: Martin Schoeberl on 24 Nov 2005 07:07 I would like to code the on-chip memory in vendor neutral VHDL. I got it running for a dual-port memory with single clock and same port sizes for the read and write port. However, I need a memory with a 32-bit write port and an 8-bit read port. So far I was not able to code it in VHDL in a way that the Synthesizer inferres the correct block ram without an extra read MUX. BTW: I do my test at the moment with Quartus. Will see how Xilinx XSE will support this. Martin
From: Martin Schoeberl on 24 Nov 2005 09:24 >I would like to code the on-chip memory in vendor neutral VHDL. > I got it running for a dual-port memory with single clock and > same port sizes for the read and write port. > > However, I need a memory with a 32-bit write port and an 8-bit > read port. So far I was not able to code it in VHDL in a way > that the Synthesizer inferres the correct block ram without > an extra read MUX. > I'll give up one this vendor independent block RAM project. For the 32-bit write data, 8-bit read data with registered address, in data and unregistered out data RAM coded in VHDL I got: On the Altera Cyclone: generates a 32-bit dual port RAM with an external 4:1 MUX. This MUX hurts fmax (from 94MHz down to 84MHz)! On the Xlinix Spartan-3: The RAM gets implemented as distributed RAM! Uses a lot of LCs and the fmax goes from 65MHz down to 50MHz So I will bite the bullet and use two vendor specific VHDL files. However, there is one open issue: I want the memory size be configurable via a generic. This is possible with Alteras altsyncram. For Xilinx I only know those RAMB16_S9_S36 components where the memory size is part of the component name. Is there a a Xilinx block RAM component where I can specify the size? Thanks, Martin
From: John Adair on 24 Nov 2005 09:41 The RAMB16 elements are the raw RAM macros. The Sx part of the name indicates the port width. You can build up bigger memories in Coregen which is a bit like the Altera Megawizard tool or build them up yourself using generic statements using the raw macros. If you looking at switching between vendors one trick is to hide a RAM inside a wrapper file. If you use the wrapper level as the RAM component for instantiation then you will only have to change the technology based memory element in one place i.e. the the wrapper file. Some synthesisers are capable of inferring RAM usually using an indexed array of something like VHDL's "std_logic_vector". I can't tell you much about the results as it isn't my own preferred method but a non-vendor synthesiser may do better than one offered by the silicon vendors. John Adair Enterpoint Ltd. - Home of FPGA PCI Development Boards. http://www.enterpoint.co.uk "Martin Schoeberl" <mschoebe(a)mail.tuwien.ac.at> wrote in message news:4385cd12$0$8024$3b214f66(a)tunews.univie.ac.at... > >I would like to code the on-chip memory in vendor neutral VHDL. >> I got it running for a dual-port memory with single clock and >> same port sizes for the read and write port. >> >> However, I need a memory with a 32-bit write port and an 8-bit >> read port. So far I was not able to code it in VHDL in a way >> that the Synthesizer inferres the correct block ram without >> an extra read MUX. >> > > I'll give up one this vendor independent block RAM project. For > the 32-bit write data, 8-bit read data with registered address, > in data and unregistered out data RAM coded in VHDL I got: > > On the Altera Cyclone: generates a 32-bit dual port RAM with an > external 4:1 MUX. This MUX hurts fmax (from 94MHz down to 84MHz)! > > On the Xlinix Spartan-3: The RAM gets implemented as distributed > RAM! Uses a lot of LCs and the fmax goes from 65MHz down to > 50MHz > > So I will bite the bullet and use two vendor specific VHDL files. > However, there is one open issue: I want the memory size be > configurable via a generic. This is possible with Alteras > altsyncram. > > For Xilinx I only know those RAMB16_S9_S36 components where > the memory size is part of the component name. Is there a > a Xilinx block RAM component where I can specify the size? > > Thanks, > Martin >
From: Aurelian Lazarut on 24 Nov 2005 09:42 Martin Schoeberl wrote: >>I would like to code the on-chip memory in vendor neutral VHDL. >>I got it running for a dual-port memory with single clock and >>same port sizes for the read and write port. >> >>However, I need a memory with a 32-bit write port and an 8-bit >>read port. So far I was not able to code it in VHDL in a way >>that the Synthesizer inferres the correct block ram without >>an extra read MUX. >> >> >> > >I'll give up one this vendor independent block RAM project. For >the 32-bit write data, 8-bit read data with registered address, >in data and unregistered out data RAM coded in VHDL I got: > >On the Altera Cyclone: generates a 32-bit dual port RAM with an >external 4:1 MUX. This MUX hurts fmax (from 94MHz down to 84MHz)! > >On the Xlinix Spartan-3: The RAM gets implemented as distributed >RAM! Uses a lot of LCs and the fmax goes from 65MHz down to >50MHz > >So I will bite the bullet and use two vendor specific VHDL files. >However, there is one open issue: I want the memory size be >configurable via a generic. This is possible with Alteras >altsyncram. > >For Xilinx I only know those RAMB16_S9_S36 components where >the memory size is part of the component name. Is there a >a Xilinx block RAM component where I can specify the size? > > NO, but you can use GENERATE (assuming VHDL) to switch between different bram geometries Aurelian >Thanks, >Martin > > > > -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
From: Martin Schoeberl on 24 Nov 2005 12:11
> The RAMB16 elements are the raw RAM macros. The Sx part of the name indicates the port width. You can build up bigger memories in > Coregen which is a bit like the Altera Megawizard tool or build them up yourself using generic statements using the raw macros. Can you describe this a little bit more specific, please? Are the other components available to describe Xilinx block RAMs? BTW: With the web edition I don't have Coregen and I also don't use the Megawizzard in Quartus. Ideal setup is a single generic parameter with the memory size (in lenght of the address). > If you looking at switching between vendors one trick is to hide a RAM inside a wrapper file. If you use the wrapper level as the > RAM component for instantiation then you will only have to change the technology based memory element in one place i.e. the the > wrapper file. That's the way I do it. I switch between technologies with different files in the project. I also use this different VHDL files in projects for other customization - primitiv, but efficient. > Some synthesisers are capable of inferring RAM usually using an indexed array of something like VHDL's "std_logic_vector". I can't > tell you much about the results as it isn't my own preferred method but a non-vendor synthesiser may do better than one offered by > the silicon vendors. The Xilinx tool interffered distributed RAM from the VHDL description. A thing I definitely don't want. Quartus had problems with the different port sizes, but single port sizes work very well. Martin >> >I would like to code the on-chip memory in vendor neutral VHDL. >>> I got it running for a dual-port memory with single clock and >>> same port sizes for the read and write port. >>> >>> However, I need a memory with a 32-bit write port and an 8-bit >>> read port. So far I was not able to code it in VHDL in a way >>> that the Synthesizer inferres the correct block ram without >>> an extra read MUX. >>> >> >> I'll give up one this vendor independent block RAM project. For >> the 32-bit write data, 8-bit read data with registered address, >> in data and unregistered out data RAM coded in VHDL I got: >> >> On the Altera Cyclone: generates a 32-bit dual port RAM with an >> external 4:1 MUX. This MUX hurts fmax (from 94MHz down to 84MHz)! >> >> On the Xlinix Spartan-3: The RAM gets implemented as distributed >> RAM! Uses a lot of LCs and the fmax goes from 65MHz down to >> 50MHz >> >> So I will bite the bullet and use two vendor specific VHDL files. >> However, there is one open issue: I want the memory size be >> configurable via a generic. This is possible with Alteras >> altsyncram. >> >> For Xilinx I only know those RAMB16_S9_S36 components where >> the memory size is part of the component name. Is there a >> a Xilinx block RAM component where I can specify the size? >> >> Thanks, >> Martin >> > > |