Slow FIFO using external SRAM
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From: damir on 29 Nov 2005 05:23 I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external single-port SRAM connected to the FPGA (Spartan II/III). Does anyone have similar FIFO controller (sync/async) implemented using VHDL? Thanks, Damir
From: Andy Peters on 29 Nov 2005 13:46 damir wrote: > I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external > single-port SRAM connected to the FPGA (Spartan II/III). > > Does anyone have similar FIFO controller (sync/async) implemented using > VHDL? A FIFO in a single-port RAM? Neat trick, although I suppose the slow speed makes it do-able. -a
From: Peter Alfke on 29 Nov 2005 14:27 I would design a reasonably fast state machine ( 50 MHz?) that keeps track of the read and write requests, updates the two addresses and multiplexes them appropriately to the external SRAM. If read-access time is important, you could always pre-fetch the next entry and store it in an on-chip register. The state machine must check for the two addresses becoming equal. If read causes them to become equal, the FIFO is empty, if write causes it, the FIFO is full. The slow speed makes all this possible, and even easy. Don't worry too much about metastability of the control circuitry. Just make sure that there is an extra 5 ns of settling-time slack available. Peter Alfke, Xilinx Applications
From: damir on 29 Nov 2005 14:53 Thanks for the hint, I'll try this approach! Damir "Peter Alfke" <peter(a)xilinx.com> wrote in message news:1133292476.312758.278240(a)f14g2000cwb.googlegroups.com... >I would design a reasonably fast state machine ( 50 MHz?) that keeps > track of the read and write requests, updates the two addresses and > multiplexes them appropriately to the external SRAM. If read-access > time is important, you could always pre-fetch the next entry and store > it in an on-chip register. The state machine must check for the two > addresses becoming equal. If read causes them to become equal, the FIFO > is empty, if write causes it, the FIFO is full. > The slow speed makes all this possible, and even easy. > Don't worry too much about metastability of the control circuitry. Just > make sure that there is an extra 5 ns of settling-time slack available. > Peter Alfke, Xilinx Applications >
From: Arlet on 29 Nov 2005 15:02
damir wrote: > I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external > single-port SRAM connected to the FPGA (Spartan II/III). > > Does anyone have similar FIFO controller (sync/async) implemented using > VHDL? > > Thanks, > > Damir I would put two small FIFOs on the FPGA, and then have a simple, synchronous state machine to control the external RAM. The state machine would look at how full/empty the FIFOs are, and based on their priority determine whether it will do a either a read or write access to the external RAM. If you need an asych FIFO, then use one of the on-chip FIFOs to cross the clock domains, and keep the rest on the same clock. |