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From: tamoruso on 11 Feb 2010 11:29
ISE drives me crazy!

One of the most powerful features of VHDL is the ability to handle
multiple architectures and configurations for the same entity. This
makes for efficient simulation, regression testing, and promotes code
reuse.

I've spent way too many hours trying to figure out problems with
ISE synthesis (XST). I have tried various permutations of
configurations, separate files for each configuration, using just
a single configuration file in the project, all to no avail. The
GUI always seems to display the incorrect architecture. Now, I
"think" this is just a GUI anomaly and in actuality the tool
knows which architecture bind. But, when you need to use the GUI
to help diagnose a synthesis problem how do you trust it? The only
thing you can do is let it rip the use the (terrible) schematic RTL
viewer to get a sense of what it did. This is not efficient if you
tend to have a heavily scripted development flow. Who wants to look
at the RTL view for every regression?


Same files, same configuration used with Synplicity and everything
is great! I always know what architecture it is going to use, and
(get this) I can select which top-level configuration to synthesize!
However many times Synplicity has difficulty closing timing or I can't
check-out a license because someone else has it tied up (but that's
rant for a later time). Plus, Synplicity is expensive compared to
ISE (OK, you get what you pay for).


It's one thing to be frustrated because I cannot get a design to
synthesize with XST. It's another problem altogether when it
synthesizes incorrectly! I spent a lot of time debugging why some
logic was getting optimized away. Turns out XST did not use the
architecture it was instructed to use at a lower level in the design.

Bottom line:
Xilinx cannot handle VHDL configuration constructs properly. So until
it does, I will have to overcome my loathing to dumb-down my code and
scripts in order to accommodate Xilinx.




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From: RCIngham on 11 Feb 2010 11:58
<snip>

>Bottom line:
>Xilinx cannot handle VHDL configuration constructs properly. So until
>it does, I will have to overcome my loathing to dumb-down my code and
>scripts in order to accommodate Xilinx.
>

The Design Manager GUI isn't clever in the way it handles conditional
generates, either. Thus I haven't told it the whereabouts of the file
containing the behavioural model of one of the sub-modules that mostly I
use when simulating, in case XST tries to synthesize it!

My experience is that synthesis tools are less smart with regards to
generates and configurations than simulators (ModelSim, at least).


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