PAL's and GAL's
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From: Jim Granville on 30 Mar 2006 02:37 Paul Burke wrote: > jozamm(a)gmail.com wrote: > >> What software is available to enter the logic equations and compile to >> the fuse file? Does any schematic entry software exist which one can >> enter the schemtic and compule to the fuse map? > > > What level education is it (school or university)? If the latter, I'd > take the plunge and go straight for one of the free HDL development > systems. Perhaps for beginners, Verilog would be easier than VHDL which > is quirky to say the least. And there are loads of examples available on > opencores.org. For the device, perhaps Xilinx Coolrunner, which are a > bit small at the affordable level. > > One disadvantage of this route is that the tools are baroque, and it > seems that the developers don't talk to each other. Students could spend > as much time getting the tools to behave as they do learning about the > devices and logic. > > If you really want the simplicity of FPGAs, something like CUPL or OPAL > could be used. They used to be free, but I doubt their availability from > manufactureres now. CUPL is still available, for free, as Atmel WinCUPL http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2759 which also includes the command line versions. CUPL is ideally suited to the GAL/PAL level the OP mentioned - where you code at the macrocell level. > If you want to go down this route, mail me and I can > send you OPALjr or one of the early Lattice schematic based ones (though > licensing might be a problem for the latter). You can use GAL or PALCE > devices- the fuse map is the same. I'd forgotten about OPALjr :) -jg
From: Didi on 30 Mar 2006 03:33 > CUPL is ideally suited to the GAL/PAL level the OP mentioned - > where you code at the macrocell level. Back in 1988/9 it was CUPL which made me write my first logic compiler (not available for windows etc.). It cost me a day to figure out why my 16V8 would not work until I discovered CUPL was not taking into account the output polarity of the feedback signals (did it right only as long as they were active high...). Fortunately, those were the days when the JTAG fusemap was listed in the datasheets so I could see what was going wrong and move forward. They may have fixed that since - I never touched it again afterwards. Perhaps still usable as a teaching tool, having access to the lower level data may be a great advantage in that respect. And well, if someone has to discover some bug yet again while learning, this will actually be advantageous, too.... Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ Jim Granville wrote: > Paul Burke wrote: > > > jozamm(a)gmail.com wrote: > > > >> What software is available to enter the logic equations and compile to > >> the fuse file? Does any schematic entry software exist which one can > >> enter the schemtic and compule to the fuse map? > > > > > > What level education is it (school or university)? If the latter, I'd > > take the plunge and go straight for one of the free HDL development > > systems. Perhaps for beginners, Verilog would be easier than VHDL which > > is quirky to say the least. And there are loads of examples available on > > opencores.org. For the device, perhaps Xilinx Coolrunner, which are a > > bit small at the affordable level. > > > > One disadvantage of this route is that the tools are baroque, and it > > seems that the developers don't talk to each other. Students could spend > > as much time getting the tools to behave as they do learning about the > > devices and logic. > > > > If you really want the simplicity of FPGAs, something like CUPL or OPAL > > could be used. They used to be free, but I doubt their availability from > > manufactureres now. > > CUPL is still available, for free, as > Atmel WinCUPL > http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2759 > > which also includes the command line versions. > > CUPL is ideally suited to the GAL/PAL level the OP mentioned - > where you code at the macrocell level. > > > If you want to go down this route, mail me and I can > > send you OPALjr or one of the early Lattice schematic based ones (though > > licensing might be a problem for the latter). You can use GAL or PALCE > > devices- the fuse map is the same. > > I'd forgotten about OPALjr :) > > -jg
From: jozamm@gmail.com on 30 Mar 2006 04:24 Hi Thanks for all the information. The only interest is more academic as i want to use them for demonsration purposes since i teach a vocational engineering course i do not only need to explain the use but even to show these devices working. I cant use VHDL or Verilog because the level is pitched too high for my students. The reason wanting schematic entry is for my students to visualize what is happening rather then the luxury of schematic entry for itself. Joseph
From: bill.sloman on 30 Mar 2006 06:09 Jim Granville wrote: > jozamm(a)gmail.com wrote: <snip> > Anachip PEEL series > http://www.anachip.com/eng/product/pld.php > Software : WinPLACE, smallish in size, Boolean equation entry. I used that for years. The PA7024 was a drop-in replacment for the 22V10 work-horse, but with enough buried cells and extra routing to be a lot more flexible. On at least one occasion I was able to rescue a board where the designer had failed to tolerance the timing inside their 22V10 by dropping in a PA7024 replacement and using most of the extra cells as delay elements. The PA7024 isn't exactly up to realising "system on a chip" applications but you can do a surprising amount of stuff with the logic it gives you. These days, I'd look for programmalbe logic parts that support in-system programming (ISP). I really like the Coolrunner parts (originally Philips, now Xilinx) but most places where I've worked have gone for Lattice parts for their low end programmable logic. -- Bill Sloman, Nijmegen
From: Jim Granville on 30 Mar 2006 06:12
jozamm(a)gmail.com wrote: > Hi > > Thanks for all the information. The only interest is more academic as i > want to use them for demonsration purposes since i teach a vocational > engineering course i do not only need to explain the use but even to > show these devices working. I cant use VHDL or Verilog because the > level is pitched too high for my students. > > The reason wanting schematic entry is for my students to visualize what > is happening rather then the luxury of schematic entry for itself. Most of the tools can create a series of TXT files, that show the morphing that takes place, and you can always draw covering drawings. CUPL outputs a .DOC file, that shows the final equations, and some intermediate ones that show the pre-parser and macro expansion results. If you use the smaller CPLDs that also use a fitter, that also creates a TXT report file, that shows how the logic finally mapped to the silicon. As a tiny example: ~~~~~~~~~~~~~~~~ CUPL .PLD source ~~~~~~~~~~~~~~~~~~~~~~ This is the Table, or simple ROM syntax - this is a 7 segment display. TABLE GCtr => [D4A,D4B,D4C,D4D,D4E,D4F,D4G] { Ca_ => Dri0; /* 0 */ Cb_ => Dri1; /* 1 */ Cc_ => Dri2; /* 2 */ Cd_ => Dri3; /* 3 */ Ce_ => Dri4; /* 4 */ Cf_ => Dri5; /* 5 */ Cg_ => Dri6; /* 6 */ Ch_ => Dri7; /* 7 */ } ~~~~~~~~~~~~~~~~ CUPL .DOC report ~~~~~~~~~~~~~~~~~~~~~~ D4A => !GCtr0 & GCtr1 & GCtr2 # GCtr0 & !GCtr1 & !GCtr2 D4B => GCtr0 & GCtr2 D4C => GCtr0 & GCtr1 & !GCtr2 D4D => !GCtr0 & GCtr2 # GCtr0 & !GCtr1 & !GCtr2 D4E => !GCtr0 & !GCtr1 & GCtr2 # GCtr0 & !GCtr1 & !GCtr2 # !GCtr0 & GCtr1 # GCtr0 & GCtr1 & GCtr2 D4F => !GCtr0 & !GCtr1 & GCtr2 # GCtr0 & !GCtr2 # !GCtr0 & GCtr1 & !GCtr2 D4G => !GCtr1 ~~~~~~~~~~~~~~~~ Atmel Fitter .FIT report ~~~~~~~~~~~~~~~~~~~~~~ Same as above, but note the D4E has optimized by flipping the logic. D4A = ((!GCtr0.Q & GCtr1.Q & GCtr2.Q) # (GCtr0.Q & !GCtr1.Q & !GCtr2.Q)); D4B = (GCtr0.Q & GCtr2.Q); D4C = (GCtr0.Q & GCtr1.Q & !GCtr2.Q); D4D = ((GCtr0.Q & !GCtr2.Q & !GCtr1.Q) # (!GCtr0.Q & GCtr2.Q)); !D4E = ((GCtr0.Q & GCtr1.Q & !GCtr2.Q) # (!GCtr0.Q & !GCtr1.Q & !GCtr2.Q) # (GCtr0.Q & !GCtr1.Q & GCtr2.Q)); D4F = ((!GCtr2.Q & GCtr1.Q) # (!GCtr0.Q & GCtr2.Q & !GCtr1.Q) # (GCtr0.Q & !GCtr2.Q)); D4G = !GCtr1.Q; |