PAL's and GAL's
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From: Jim Stewart on 31 Mar 2006 12:37 Paul Burke wrote: > John Larkin wrote: > >> >> I'm currently doing a PEEL 22CV10 design > > > They are beautiful devices, worlds better than GALs. A rich choice of > feedback (you can configure an embedded flipflop, and use the associated > pin as an input) and the clock is fed into the product matrix. Sad that > they never really caught on, and I'm not sure that anyone else ever made > them. Though ICT did irritate me badly by changing the programming > algorithm just after the manufacturer of my programmer stopped > supporting that model. Another PEEL lover. I thought I was alone in the world. Very nice devices and never had a lick of trouble with them.
From: CBFalconer on 31 Mar 2006 06:18 Joel Kolstad wrote: > "Nico Coesel" <nico(a)puntnl.niks> wrote in message > >> Its good to use both schematics and VHDL in an FPGA design. > > Yes, I agree with you. The point I was trying to make -- pretty > poorly given how I worded it -- was that these days a schematic > symbol such as an AND gate gets mapped to some VHDL or Verilog > code, which then gets synthesized down to primitives & > placed/routed. Whereas historically the AND gate was, itself, a > primitive. Only to those who didn't minimize logic in the first place. The old fashioned way was to generate minimized logic equations from Karnaugh maps, and then implement that with gates. -- "If you want to post a followup via groups.google.com, don't use the broken "Reply" link at the bottom of the article. Click on "show options" at the top of the article, then click on the "Reply" at the bottom of the article headers." - Keith Thompson More details at: <http://cfaj.freeshell.org/google/> Also see <http://www.safalra.com/special/googlegroupsreply/>
From: John Larkin on 31 Mar 2006 13:03 On Fri, 31 Mar 2006 09:37:07 -0800, Jim Stewart <jstewart(a)jkmicro.com> wrote: >Paul Burke wrote: >> John Larkin wrote: >> >>> >>> I'm currently doing a PEEL 22CV10 design >> >> >> They are beautiful devices, worlds better than GALs. A rich choice of >> feedback (you can configure an embedded flipflop, and use the associated >> pin as an input) and the clock is fed into the product matrix. Sad that >> they never really caught on, and I'm not sure that anyone else ever made >> them. Though ICT did irritate me badly by changing the programming >> algorithm just after the manufacturer of my programmer stopped >> supporting that model. > >Another PEEL lover. I thought I was alone >in the world. Very nice devices and never >had a lick of trouble with them. > They're handy. Nice 5-volt logic blocks. Production can program and label a tube of them at the programming station, and later plug them into sockets on boards without all that JTAG nonsense. John
From: Jonathan Kirwan on 1 Apr 2006 15:15 On Fri, 31 Mar 2006 10:18:22 +1200, Jim Granville <no.spam(a)designtools.co.nz> wrote: > To clarify, with some of the design constructs we use, I have no idea >how one would draw them with any clarity in a schematic, so to me that >will always be a subset-flow. > > Where I can see a strong case, is for using Spice/Schematics in the >simulation side of the design flow. - ie use your tools to their strengths. Elsewhere on sci.electronics.design: > On 31 Mar 2006 23:16:59 -0800, "slebetman(a)yahoo.com" <slebetman(a)gmail.com> wrote: > > >I use Digital Works to test my CPU designs. It used to be sold by > >mecanique (www.mecanique.co.uk) but they no longer sell it nor make it > >available for download. There is still a copy of version 3.04 at: > > > > http://www.electronics-lab.com/downloads/schematic/002/index.html > > > >But I don't use this version. Instead I use the freeware version (2.0) > >available at: > > > > http://www.spsu.edu/cs/faculty/bbrown/circuits/howto.html > > > >As far as I can tell the only real difference between version 2.0 and > >version 3.0 is that version 3.0 is no longer freeware. Also, files > >created in version 3.0 are not compatible with version 2.0. > > > >What I like about Digital Works is that the RAM/ROM object has a built > >in, easy to use hex editor. Otherwise, if I don't need to use RAM or > >ROM I prefer Logisim: > > > > http://ozark.hendrix.edu/~burch/logisim/ > > > >which is even nicer for complex designs because it supports busses. But > >its RAM/ROM interface sucks. The latter, logisim, allows a bus. It's also at SourceForge, so modifications to it to support what's needed not only for simulation of the logic but also then creating a fuse map are possible, I'd suppose. I have used VHDL and Verilog with some CPLD and FPGA parts and have enjoyed that. But I haven't had to do PAL and GAL programming with PALASM or CUPL. So my ignorance allows me to imagine that a good, free graphical tool could be applied to good purpose in teaching. In any case, there hasn't been enough of a response from the OP. So I should bite my tongue, I suppose. Jon
From: Jim Granville on 1 Apr 2006 17:04
Jonathan Kirwan wrote: > On Fri, 31 Mar 2006 10:18:22 +1200, Jim Granville > <no.spam(a)designtools.co.nz> wrote: > > >> To clarify, with some of the design constructs we use, I have no idea >>how one would draw them with any clarity in a schematic, so to me that >>will always be a subset-flow. >> >> Where I can see a strong case, is for using Spice/Schematics in the >>simulation side of the design flow. - ie use your tools to their strengths. > > > Elsewhere on sci.electronics.design: > > >> On 31 Mar 2006 23:16:59 -0800, "slebetman(a)yahoo.com" <slebetman(a)gmail.com> wrote: >> >> >I use Digital Works to test my CPU designs. It used to be sold by >> >mecanique (www.mecanique.co.uk) but they no longer sell it nor make it >> >available for download. There is still a copy of version 3.04 at: >> > >> > http://www.electronics-lab.com/downloads/schematic/002/index.html >> > >> >But I don't use this version. Instead I use the freeware version (2.0) >> >available at: >> > >> > http://www.spsu.edu/cs/faculty/bbrown/circuits/howto.html >> > >> >As far as I can tell the only real difference between version 2.0 and >> >version 3.0 is that version 3.0 is no longer freeware. Also, files >> >created in version 3.0 are not compatible with version 2.0. >> > >> >What I like about Digital Works is that the RAM/ROM object has a built >> >in, easy to use hex editor. Otherwise, if I don't need to use RAM or >> >ROM I prefer Logisim: >> > >> > http://ozark.hendrix.edu/~burch/logisim/ >> > >> >which is even nicer for complex designs because it supports busses. But >> >its RAM/ROM interface sucks. > > > The latter, logisim, allows a bus. It's also at SourceForge, so > modifications to it to support what's needed not only for simulation > of the logic but also then creating a fuse map are possible, I'd > suppose. Interesting, I've book marked that. The OP could use this to get the ideas across, then code in CUPL. Seems logism is purely digital, so misses my target of mixed-simulation, but I can see it could expand in that domain by : a) Adding EQN output ( also needs library work ) ? These libraries then tend to restrict the flow to specific back ends. b) Adding table SIM output, in JED.Vector syntax, which would append to the JED file created by the other flow Doing the latter would give some interesting parallel paths. c) Add an ASCII export, so you can paste into TEXT based source ? > I have used VHDL and Verilog with some CPLD and FPGA parts and have > enjoyed that. But I haven't had to do PAL and GAL programming with > PALASM or CUPL. So my ignorance allows me to imagine that a good, > free graphical tool could be applied to good purpose in teaching. The above logisim looks useful for that. > In any case, there hasn't been enough of a response from the OP. So I > should bite my tongue, I suppose. Well, he now has many suggestions to follow up on. :) My present area is pushing PLDs into mixed-signal space, and this will be using a good graphical tool for the teaching (Spice). I will not be (initially) pushing for this as a whole flow, for the reasons previously mentioned, but will focus on the areas where there are presently no tools at all. Another drawback of Schematic Entry, is you tend to get binary format source files, that can have lifetime dead-ends. See some of the threads in Comp.arch.fpga on this issue.... -jg |