PCB trace spacing with soldermask
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From: oparr on 16 May 2010 08:55 > I guess that depends on how you interpret "for voltages up to 100VDC". 3V is > certainly below 100V. And if 3V is all the device needs to handle then a commensurate device package would be used. The device package the manufacturer chooses usually takes into consideration the device voltage rating. Even if a relatively fine pitch package is associated with a relatively high voltage (100V transistor arrays for example), it's hardly likely that you'll find collector and emitter terminals adjacent for example. There is only one sensible way to interpret "for voltages up to 100VDC" IMO.....A spacing suitable for the highest voltage in the range which would be 100VDC. On May 15, 11:15 pm, "k...(a)att.bizzzzzzzzzzzz" <k...(a)att.bizzzzzzzzzzzz> wrote: >
From: krw on 16 May 2010 13:07 On Sun, 16 May 2010 05:55:00 -0700 (PDT), "oparr(a)hotmail.com" <oparr(a)hotmail.com> wrote: >> I guess that depends on how you interpret "for voltages up to 100VDC". 3V is >> certainly below 100V. > >And if 3V is all the device needs to handle then a commensurate device >package would be used. The device package the manufacturer chooses >usually takes into consideration the device voltage rating. Even if a >relatively fine pitch package is associated with a relatively high >voltage (100V transistor arrays for example), it's hardly likely that >you'll find collector and emitter terminals adjacent for example. Try reading, this time with your brain turned on. >There is only one sensible way to interpret "for voltages up to >100VDC" IMO.....A spacing suitable for the highest voltage in the >range which would be 100VDC. Wrong. This phrase can also be read as "these groundrules apply for all voltages up to 100V".
From: Paul Keinanen on 16 May 2010 13:56 On Sat, 15 May 2010 08:05:23 -0700 (PDT), "oparr(a)hotmail.com" <oparr(a)hotmail.com> wrote: >A certain trace spacing guideline is indicating a minimum requirement >of .005" spacing for voltages up to 100VDC for soldermasked traces. Is >that correct? Any caveats? Are you referring to some internally generated 100 VDC from a high impedance source or perhaps some external signal conductors (such as the telephone circuitry) or even some rectified mains ? When dealing with tracks that are connected to some external wiring (such as mains or telephone) one should expect much larger peak voltages than the nominal voltage. In Europe on the ordinary 230/400 Vac mains feed, the system is expected to tolerate 1.5 kV peak voltages, thus the PCB track separation must be considerable.
From: oparr on 16 May 2010 17:09 > Are you referring to some internally generated 100 VDC from a high > impedance source or perhaps some external signal conductors (such as > the telephone circuitry) or even some rectified mains ? Assume a voltage of 100VDC or 100V peak. On May 16, 1:56 pm, Paul Keinanen <keina...(a)sci.fi> wrote: >
From: oparr on 16 May 2010 17:21
> We found that even with 4mil spacing breakdown didn't occur until > about 2KV for surface traces and about KV for buried traces on > ordinary FR4. Kevin, thanks. Information like this, to me at least, can be more valuable than what some table or calculator returns IMO. On May 16, 1:03 pm, kevin93 <ke...(a)whitedigs.com> wrote: > |