PCB trace spacing with soldermask
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From: oparr on 15 May 2010 11:05 A certain trace spacing guideline is indicating a minimum requirement of .005" spacing for voltages up to 100VDC for soldermasked traces. Is that correct? Any caveats?
From: qrk on 15 May 2010 13:50 On Sat, 15 May 2010 08:05:23 -0700 (PDT), "oparr(a)hotmail.com" <oparr(a)hotmail.com> wrote: >A certain trace spacing guideline is indicating a minimum requirement >of .005" spacing for voltages up to 100VDC for soldermasked traces. Is >that correct? Any caveats? According to my old Bishop Graphics catalog, coated traces at 100V, spacing should be 0.020" minimum. This chart is based off MIL-STD-275D. 5 mils for 100V doesn't sound right. -- Mark
From: oparr on 15 May 2010 14:22 > According to my old Bishop Graphics catalog, coated traces at 100V, > spacing should be 0.020" minimum. This chart is based off > MIL-STD-275D. 5 mils for 100V doesn't sound right. I'm seeing a lot of conflicting advice. Somewhere I recall seeing .2mm (.008") spacing being good for up to 100VDC. At the link below, the Gecko drive fellow (Mariss Freimanis) indicates that .0125" is fine for 100VDC; http://finance.groups.yahoo.com/group/geckodrive/message/4674 On May 15, 1:50 pm, qrk <SpamT...(a)spam.net> wrote: >
From: a7yvm109gf5d1 on 15 May 2010 17:51 On May 15, 10:05 am, "op...(a)hotmail.com" <op...(a)hotmail.com> wrote: > A certain trace spacing guideline is indicating a minimum requirement > of .005" spacing for voltages up to 100VDC for soldermasked traces. Is > that correct? Any caveats? Are you sure that wasn't 0.5mm?
From: langwadt on 15 May 2010 18:15
On 15 Maj, 17:05, "op...(a)hotmail.com" <op...(a)hotmail.com> wrote: > A certain trace spacing guideline is indicating a minimum requirement > of .005" spacing for voltages up to 100VDC for soldermasked traces. Is > that correct? Any caveats? first hit on google: http://www.smps.us/pcbtracespacing.html -LAsse |