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From: Ghostboy on 3 May 2010 14:59
Hi,

I have some problems to let the FPGA generate an interrupt and to detect
this interrupt on the computer (via PCI).

Below you find a part of the VHDL-code from the PCI core generated by
Xilinx Core Generator. Everytime data is written on the PCI bus the
interrupt (INTR_N) will be asserted.

Beneath that there is a part of the c-code from the device driver file I
made in Linux (Ubuntu). So everytime it detects an interrupt from the FPGA,
it will add one to the counter (IRQ_count).

The problem I have is that the counter remains 0. Someone knows what could
be wrong? Is there a problem with the code or am I using the wrong
interrupt signal? I hope someone can help me. I can send data to the FPGA
via the pc so I presume there is no problem with the connection between
both hardware devices.

Thanks in advance!

--------------------------------------
--- PCI CORE / IO32 Implementation ---
--------------------------------------

WRITE_MY_IO_REG:
process(RST, CLK)
begin
if RST = '1' then my_io_reg <= "00010000000100000001000000010000";
intr_n_reg <= '0';

elsif (CLK'event and CLK = '1') then

if S_DATA_VLD = '1' and bar0_wr_cs = '1' then

intr_n_reg <= '1';

if S_CBE(0) = '0' then my_io_reg( 7 downto 0) <= ADIO( 7 downto
0);
end if;
if S_CBE(1) = '0' then my_io_reg(15 downto 8) <= ADIO(15 downto
8);
end if;
if S_CBE(2) = '0' then my_io_reg(23 downto 16) <= ADIO(23 downto
16);
end if;
if S_CBE(3) = '0' then my_io_reg(31 downto 24) <= ADIO(31 downto
24);
end if;

else intr_n_reg <= '0';

end if;
end if;
end process;

INTR_N <= intr_n_reg;

oe_io_reg <= bar0_rd_cs and S_DATA;
ADIO <= my_io_reg when (oe_io_reg = '1') else (others=>'Z');


---------------------------------------
--- Linux Device Driver / Interrupt ---
---------------------------------------

irqreturn_t pci_interrupt_handler(int irq, void *dev_id)
{

irq_count = irq_count + 1;

printk(KERN_INFO "Virtex 2 PRO Interrupt detected %i\n", irq_count);

return IRQ_HANDLED;
}






---------------------------------------
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From: Nico Coesel on 3 May 2010 15:59
"Ghostboy" <Ghostboy(a)n_o_s_p_a_m.n_o_s_p_a_m.dommel.be> wrote:

>Hi,
>
>I have some problems to let the FPGA generate an interrupt and to detect
>this interrupt on the computer (via PCI).
>
>Below you find a part of the VHDL-code from the PCI core generated by
>Xilinx Core Generator. Everytime data is written on the PCI bus the
>interrupt (INTR_N) will be asserted.

Aren't there 4 interrupt pins on a PCI slot (INT_A through INT_D)?
Maybe you're triggering the wrong pin.

You should also be able to see the interrupt count in /proc/interrupts


--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico(a)nctdevpuntnl (punt=.)
--------------------------------------------------------------
From: Ghostboy on 4 May 2010 07:16
The data sheet of the PCI core says that you can use INTR_N from within the
user application to make an interrupt. But I must admit that I can't see a
connection to the bus. There is indeed also INTR_A but I can't find a way
to connect it to INTR_N.


---------------------------------------
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