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From: Alex on 7 Dec 2005 13:14
Hello,

I am trying to use PLX9056 as an interface between PCI bus and local bus, in
manner as simple as possible. I would fill some SRAM on the local bus with
certain amount of data (256 or 8K or 32K or 64K words) from uP or FPGA and
then tell PLX to take that data and transfer it to PCI bus. The transfer may
also need to go in the opposite direction, i.e. PLX filling the SRAM and
telling my uP/FPGA that the data is ready. Arbitration may be handled on
local bus side by an FPGA, but I do not know how to establish the
communication between uP/FPGA and PLX.

Is there a group of registers where size of data for burst transfer can be
defined? How to tell PLX that the data is ready for transfer? How does the
PLX tell uP/FPGA on local bus that data has arrived from PCI bus?

Help would be greatly appreciated.

Regards,

Alex


From: Alan Nishioka on 7 Dec 2005 15:03
Alex wrote:
> I am trying to use PLX9056 as an interface between PCI bus and local bus

I like the PLX chips. I have used the 9060 and the 9054.


> Is there a group of registers where size of data for burst transfer can be
> defined?

Use the dma engine on the plx chip. The chip has registers to set up
source, destination and size.


> How to tell PLX that the data is ready for transfer?

Set the register to start the dma.


> How does the PLX tell uP/FPGA on local bus that data has arrived from PCI bus?

You have many options:
1. Use the mailboxes in the plx chip. Interrupt or polled.
2. Use a register in the fpga. Interrupt or polled.
3. Set the dma to write a location in memory when done and poll that.
4. Poll the dma registers to see when dma is done.
5. Set the dma to interrupt when done.
6. Use EOT# end of transfer pin.

PLX has an sdk so you don't even have to write a windows driver.

Alan Nishioka

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