Prev: Drigmorn3 - Spartan-6 Board Update
Next: Spice simulation of IBIS details - model examples
From: Jason Thibodeau on 4 Mar 2010 16:20
On 02/27/2010 08:52 AM, John_H wrote:
> On Feb 26, 4:52 pm, Jason Thibodeau<jason.p.thibod...(a)gmail.com>
> wrote:
>> Hello,
>>
>> I am using Xilinx ISE 11.1, and I need to place some components in
>> certain areas of the FPGA. I have never done manual PaR, so here are a
>> few questions:
>> 1) Do I need to manually place each and every net?
>> 2) Is it possible to just place 'blocks' of each component in a general
>> area of CLB on the device, and let the PaR algorithms auto route any
>> connecting nets?
>>
>> Thanks in advance,
>> Jason
>
> You can also use the User Constraints File to explicitly place
> individual elemens using a LOC constraint or associate many components
> into an AREA_GROUP constraint.
>
> Check out the Constraints Guide at http://bit.ly/8YkuR9 for the
> details.

I am finally working on this, and I have a question.

I am inside PlanAhead. I have created a Pblock names sensor_1. I am
attempting to add all of instance U0, U1 and U2 to the pblock.

I am starting with U0. I have instances such as: U0/count_clock_0,
U0/count_clock_1 etc.

I want to add ALL of U0 to the pblock I have created. Is there some
wildcard i can use to add all the instances beginning with U0? Such as:

hdi::pblock addInstance -project ring_sensor -floorplan floorplan_1
-name sensor_1 -instance U0/* -clearLocs yes

This doesn't work, as it doesn't accept the wildcard.

Should I just Shift+click until all of U0 is selected in the netlist
window, and drag+drop from there?

Thanks in advance.
--
Jason Thibodeau
www.jayt.org
First  |  Prev  | 
Pages: 1 2
Prev: Drigmorn3 - Spartan-6 Board Update
Next: Spice simulation of IBIS details - model examples