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From: Jason Thibodeau on 26 Feb 2010 16:52
Hello,

I am using Xilinx ISE 11.1, and I need to place some components in
certain areas of the FPGA. I have never done manual PaR, so here are a
few questions:
1) Do I need to manually place each and every net?
2) Is it possible to just place 'blocks' of each component in a general
area of CLB on the device, and let the PaR algorithms auto route any
connecting nets?

Thanks in advance,
Jason
From: maxascent on 27 Feb 2010 03:42
You can just use PlanAhead to constrain your logic to a specific area of
the fpga, then just let p&r do its job.

Jon

---------------------------------------
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From: John_H on 27 Feb 2010 08:52
On Feb 26, 4:52 pm, Jason Thibodeau <jason.p.thibod...(a)gmail.com>
wrote:
> Hello,
>
> I am using Xilinx ISE 11.1, and I need to place some components in
> certain areas of the FPGA. I have never done manual PaR, so here are a
> few questions:
> 1) Do I need to manually place each and every net?
> 2) Is it possible to just place 'blocks' of each component in a general
> area of CLB on the device, and let the PaR algorithms auto route any
> connecting nets?
>
> Thanks in advance,
> Jason

You can also use the User Constraints File to explicitly place
individual elemens using a LOC constraint or associate many components
into an AREA_GROUP constraint.

Check out the Constraints Guide at http://bit.ly/8YkuR9 for the
details.
From: Jason Thibodeau on 27 Feb 2010 09:45
On 02/27/2010 08:52 AM, John_H wrote:
> On Feb 26, 4:52 pm, Jason Thibodeau<jason.p.thibod...(a)gmail.com>
> wrote:
>> Hello,
>>
>> I am using Xilinx ISE 11.1, and I need to place some components in
>> certain areas of the FPGA. I have never done manual PaR, so here are a
>> few questions:
>> 1) Do I need to manually place each and every net?
>> 2) Is it possible to just place 'blocks' of each component in a general
>> area of CLB on the device, and let the PaR algorithms auto route any
>> connecting nets?
>>
>> Thanks in advance,
>> Jason
>
> You can also use the User Constraints File to explicitly place
> individual elemens using a LOC constraint or associate many components
> into an AREA_GROUP constraint.
>
> Check out the Constraints Guide at http://bit.ly/8YkuR9 for the
> details.


Thanks for all the help, everyone. I have a lot to read up on. I'll be
working on this in the next few days, you'll probably hear from me if I
can't seen to get it working.

Sincerely,
Jason
From: rickman on 28 Feb 2010 13:12
On Feb 27, 9:45 am, Jason Thibodeau <jason.p.thibod...(a)gmail.com>
wrote:
> On 02/27/2010 08:52 AM, John_H wrote:
>
>
>
> > On Feb 26, 4:52 pm, Jason Thibodeau<jason.p.thibod...(a)gmail.com>
> > wrote:
> >> Hello,
>
> >> I am using Xilinx ISE 11.1, and I need to place some components in
> >> certain areas of the FPGA. I have never done manual PaR, so here are a
> >> few questions:
> >> 1) Do I need to manually place each and every net?
> >> 2) Is it possible to just place 'blocks' of each component in a general
> >> area of CLB on the device, and let the PaR algorithms auto route any
> >> connecting nets?
>
> >> Thanks in advance,
> >> Jason
>
> > You can also use the User Constraints File to explicitly place
> > individual elemens using a LOC constraint or associate many components
> > into an AREA_GROUP constraint.
>
> > Check out the Constraints Guide athttp://bit.ly/8YkuR9for the
> > details.
>
> Thanks for all the help, everyone. I have a lot to read up on. I'll be
> working on this in the next few days, you'll probably hear from me if I
> can't seen to get it working.
>
> Sincerely,
> Jason

Just be sure to have a final HDL design before you bother with the P&R
issues. P&R can need to be redone anytime you make code changes. So
reworking code after you've done manual P&R can be very expensive.

Rick
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