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From: Michael Dales on 31 May 2006 05:42
Hey there,

I'm trying to simulate a design generated with EDK 7.1 that uses the
plb_gemac core (version 1.01.a). When I try and load the design into
Modelsim SE (using generate simulation hdl files, then export to proj
nav, and using a testbench added to the proj nav project), the loading
fails on the plb_gemac part, claiming there is "no default binding for
component at u0". A full output of the model sim warning can be seen
below.

I've tried generating a new EDK project with just a plb_gemac in
addition to the usual ppc/bram/plb/uart bits, and I get the same error.
Any suggestions as to where I might be going wrong?

-- Michael

# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_gemac_v1_01_a/.reclock_align(structural)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fd(fd_v)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_gemac_v1_01_a/.cntr14bit8(imp)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_gemac_v1_01_a/.cntr14bit1(imp)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.prims_constants_v4_0
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.prims_comps_v4_0
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.async_fifo_v4_0_pkg(body)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.async_fifo_v4_0_components
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_gemac_v1_01_a/.tx_afifo(imp)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.async_fifo_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_dist_mem_v5_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.blkmemdp_pkg_v4_0(body)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.blkmemdp_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.memory_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.ul_utils(body)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.mem_init_file_pack_v4_0(body)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.blkmemdp_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.fifoctlr_ns_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_gate_bit_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.and_a_notb_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.prims_utils_v4_0(body)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_reg_fd_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_gate_bit_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.and_a_notb_fd_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_reg_fd_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_counter_binary_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.bcount_up_ainit_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_addsub_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_compare_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_mux_bus_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_counter_binary_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_addsub_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_mux_bus_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_gate_bus_v4_0_comp
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.binary_to_gray_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.c_gate_bus_v4_0(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.empty_flag_reg_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.reg_ainit_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/XilinxCoreLib/.full_flag_reg_v4(behavioral)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_gemac_v1_01_a/.byteshiftout(imp)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_gemac_v1_01_a/.rx_afifo(imp)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_gemac_v1_01_a/.byteshiftin(imp)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.emac(emac_v)
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_include_miim' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_miim_clkdvd' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_include_half_duplex' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_mac_fifo_depth' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_family' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_block_type' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_revision' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_minor_version' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_major_version' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3733) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Generic 'c_blk_id' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'mgmntenbl' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'clk' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rst' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rx_length_notempty' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_status_notempty' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tlrinternalrd' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_length_overrun' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_length_underrun' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rx_length_overrun' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rx_length_underrun' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_status_overrun' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_status_underrun' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rxlengthfull' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'txstatusfull' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tppr_regout' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rx_length' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_status_in' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'ifgp_regout' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'emac_control_regout' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'cea_locout' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'cea_regout' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'sa_regout' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_length_regout' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rx_done' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'start_tx' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rxchannelreset' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'tx_done' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'txlengthempty' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'internalwrapen' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'phy_rd_wr_n' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'phy_mii_clk' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'miidatafromphy' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'miidatatophy' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'ip2dma_txlengthfull' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'ip2dma_rxlengthempty' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'ip2dma_txstatusempty' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rfifo2ip_full' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'rfifo2ip_wrack' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'wfifo2ip_rdack' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'wfifo2ip_data' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'ip2bus_rdack' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'ip2bus_wrack' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'ip2bus_data' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'bus2ip_freeze' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'bus2ip_data' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'bus2ip_regwrce' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# ** Error: (vsim-3732) ./hdl/src/vhdl/xemac.vhd(2143): No default
binding for component at 'u0'.
# (Port 'bus2ip_regrdce' is not on the entity.)
# Region: /testbench_vhd/uut/plb_gemac_0/plb_gemac_0/u0/u0
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.emac_swift_bus(emac_swift_bus_v)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/plb_ipif_v2_01_a/.plb_ipif(implementation)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.inv(inv_v)
# Loading
C:/Xilinx/libs/simlib/EDK7.1.2_mti_se_nt/ISE_Lib/unisim/.fddrrse(fddrrse_v)
# Loading work.dcm_module_0_wrapper(structure)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO C:\SWIFT\gemac_sim_test\projnav\projnav.do PAUSED at line 4

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