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From: gary on 2 Jul 2006 09:04
hi,
Iam trying to instantiate a component from my user_logic_ip.vhd :

signal h:std_logic_vector(0 to 31);
signal k:std_logic_vector(0 to 31);
component inv
port( x: in std_logic_vector(0 to 31);
z: out std_logic_vector(0 to 31));
end component;
begin
call: inv
portmap(h,k);
iam giving these h & k values to slv_reg0 & slv_reg1
because i want to give my input from 'C' and see my output on hyper
terminal.
iam using spartan-3 starter kit for download.
In ISE Synthesize is going fine but when iam implementing design following
warnings & errors are coming:

NgdBuild:889 - Pad net 'k<10>' is not connected to an external port in
this design. A new port 'k<10>' has been added and is connected to
this
signal.
WARNING:NgdBuild:889 - Pad net 'k<4>' is not connected to an external port
in
this design. A new port 'k<4>' has been added and is connected to
this
signal.
WARNING:NgdBuild:889 - Pad net 'k<6>' is not connected to an external port
in
this design. A new port 'k<6>' has been added and is connected to
this
signal.

---------------------all k<0> to k<31>------------------------

ERROR:
NgdBuild:809 - output pad net 'k<10>' has an illegal load:
pin I2 on block IP2Bus_Data<10>1 with type LUT3
ERROR:NgdBuild:809 - output pad net 'k<4>' has an illegal load:
pin I2 on block IP2Bus_Data<4>1 with type LUT3
ERROR:NgdBuild:809 - output pad net 'k<6>' has an illegal load:
pin I2 on block IP2Bus_Data<6>1 with type LUT3

--------------------all k<0> to k<31>------------------------

i dont understand what these errors mean......
can anybody help me...........
regards
gary



From: MM on 2 Jul 2006 10:35
Could you upload your vhdl file to somewhere?

/Mikhail



From: gary on 2 Jul 2006 20:25
>Could you upload your vhdl file to somewhere?
>
>/Mikhail
>
u want to see the instantiated file it is just a inverter ...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inverter is
Port ( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end inverter;

architecture Behavioral of inverter is

begin
t<=not s;

end Behavioral;

this inverter is called in my userip.vhd file .......

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic

------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 2);
signal slv_reg_read_select : std_logic_vector(0 to 2);
signal slv_ip2bus_data : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal h : std_logic_vector(0 to 31);
signal k : std_logic_vector(0 to 31);
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;

attribute box_type : string;
attribute box_type of inverter : component is "black_box";

begin

we: inverter
port map(h,k);

/gary

From: MM on 3 Jul 2006 14:33
"gary" <rgarik(a)yahoo.com> wrote in message
news:H4CdnVAPvfF8_jXZRVn_vA(a)giganews.com...
> u want to see the instantiated file it is just a inverter ...

No, I wanted to see your userip.vhd, in particular what you are doing with h
and k, how they get assigned, etc.

Does the implementation work with the original (wizard generated)
userip.vhd?

/Mikhail


From: gary on 3 Jul 2006 20:04
>"gary" <rgarik(a)yahoo.com> wrote in message
>news:H4CdnVAPvfF8_jXZRVn_vA(a)giganews.com...
>> u want to see the instantiated file it is just a inverter ...
>
>No, I wanted to see your userip.vhd, in particular what you are doing
with h
>and k, how they get assigned, etc.
>
>Does the implementation work with the original (wizard generated)
>userip.vhd?
>
>/Mikhail
>
>hi,
Iam giving the h,k values to the regesters (slv_reg0,slv_reg1), so
that i can throw the input value from the 'C' code to the inverter & see
the output of the inverter value on the hyper terminal.


Following is my user_ip.vhd file..
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user
logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for user
logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user
logic
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Ack -- IP to Bus acknowledgement
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
------------------------------------------------------------------------------

entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 3
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to
C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to
C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to
C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to
C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to
C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);

end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

--USER signal declarations added here, as needed for user logic

------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 2);
signal slv_reg_read_select : std_logic_vector(0 to 2);
signal slv_ip2bus_data : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal h : std_logic_vector(0 to 31);
signal k : std_logic_vector(0 to 31);
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;

begin

we: inverter
port map(h,k);

--USER logic implementation added here

------------------------------------------
-- Example code to read/write user logic slave model s/w accessible
registers
--
-- Note:
-- The example code presented here is to show you one way of
reading/writing
-- software accessible registers implemented in the user logic slave
model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
-- to one software accessible register by the top level template. For
example,
-- if you have four 32 bit software accessible registers in the user
logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 2);
slv_reg_read_select <= Bus2IP_RdCE(0 to 2);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or
Bus2IP_WrCE(2);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or
Bus2IP_RdCE(2);

-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin

if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
else
case slv_reg_write_select is
when "100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "001" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;

end process SLAVE_REG_WRITE_PROC;

-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1,h,k,slv_reg2 ) is
begin

case slv_reg_read_select is
when "100" => slv_ip2bus_data <= h;
when "010" => slv_ip2bus_data <= k;
when "001" => slv_ip2bus_data <= slv_reg2;
when others => slv_ip2bus_data <= (others => '0');
end case;

end process SLAVE_REG_READ_PROC;

------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;

IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';

end IMP;

//regards
//gary




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