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From: WangoTango on 3 Feb 2010 11:36
In article <5KudnXWA2Ojb_PTWnZ2dnUVZ_oednZ2d(a)giganews.com>,
bogdanrosandic(a)n_o_s_p_a_m.gmail.com says...
> >brOS wrote:
> >> I am testing my own kernel for MSP430. I am measuring highest frequency
> for
> >> square signal that MSP430 with my kernel can repeat on its output.
> >> Square signal is connected to one of the interrupt pins, so on every
> high
> >> to low or low to high signal edge port interrupt is generated. In port
> ISR
> >> I am releasing semaphore on which my task is blocked. After task is
> >> unblocked its job is to toggle one pin declared as output. So i want to
> >> found out what is the highest frequency when no pulsed is missed to be
> >> repeated on the output pin.
> >>
> >> While i was doing my test I found out that there are frequencies where
> >> stack overflow appears(everz task has its stack where context is
> saved).
> >> The thing is that when my Scheduler switches context back to idle task,
> >> because interrupt rate is so high, it never have a chance to pop PC.
> >> That part of code looks like this
> >
> >Some kernel operations need to be done with interrupts disabled. After
> your
> >task suspends itself on the semaphore, the kernel should not be
> interruptable
> >until the next (idle) task is running. Generally, interrupts are
> reenabled by
> >executing a RETI, which restores the status register, including the GIE
> >interrupt enable bit. At that point your PC has been popped.
> >
> >--
> >Thad
> >
>
> But, is the RETI instruction atomic? I think it s not?

I never really thought about it, but I would think it would HAVE to be.
Since there would be no PC counter change until any popping of registers
(like the PC) how could you interrupt it? Maybe I am missing something
here, but if you in the middle of servicing the RETI how would you know
where to return to if 'it' were interrupted?

From: Grant Edwards on 3 Feb 2010 12:52
On 2010-02-03, brOS <bogdanrosandic(a)n_o_s_p_a_m.gmail.com> wrote:

> But, is the RETI instruction atomic? I think it s not?

Of course it is.

--
Grant Edwards grante Yow! I just had my entire
at INTESTINAL TRACT coated
visi.com with TEFLON!
From: Didi on 3 Feb 2010 14:04
On Feb 3, 6:36 pm, WangoTango <Asgar...(a)mindspring.com> wrote:
> In article <5KudnXWA2Ojb_PTWnZ2dnUVZ_oedn...(a)giganews.com>,
> bogdanrosandic(a)n_o_s_p_a_m.gmail.com says...
>
>
>
> > >brOS wrote:
> > >> I am testing my own kernel for MSP430. I am measuring highest frequency
> > for
> > >>   square signal  that MSP430 with my kernel can repeat on its output.
> > >> Square signal is connected to one of the interrupt pins, so on every
> > high
> > >> to low or low to high signal edge port interrupt is generated. In port
> > ISR
> > >> I am releasing semaphore on which my task is blocked. After task is
> > >> unblocked its job is to toggle one pin declared as output. So i want to
> > >> found out what is the highest frequency when no pulsed is missed to be
> > >> repeated on the output pin.
>
> > >> While i was doing my test I found out that there are frequencies where
> > >> stack overflow appears(everz task has its stack where context is
> > saved).
> > >> The thing is that when my Scheduler switches context back to idle task,
> > >> because interrupt rate is so high, it never have a chance to pop PC.
> > >> That part of code looks like this
>
> > >Some kernel operations need to be done with interrupts disabled.  After
> > your
> > >task suspends itself on the semaphore,  the kernel should not be
> > interruptable
> > >until the next (idle) task is running.  Generally, interrupts are
> > reenabled by
> > >executing a RETI, which restores the status register, including the GIE
> > >interrupt enable bit.  At that point your PC has been popped.
>
> > >--
> > >Thad
>
> > But, is the RETI instruction atomic? I think it s not?        
>
> I never really thought about it, but I would think it would HAVE to be.
> Since there would be no PC counter change until any popping of registers
> (like the PC) how could you interrupt it?  Maybe I am missing something
> here, but if you in the middle of servicing the RETI how would you know
> where to return to if 'it' were interrupted?  

In the context of a single bus master - the processor core - any
instruction
is atomic on all processors I know.
Things are quite different when there are multiple bus masters,
typically
there is one or 2 (or 3, as on the 68020...) "atomic" opcodes, the
rest
are not.

Dimiter

------------------------------------------------------
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http://www.tgi-sci.com
------------------------------------------------------
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From: Vladimir Vassilevsky on 3 Feb 2010 14:56


Didi wrote:

> In the context of a single bus master - the processor core - any
> instruction is atomic on all processors I know.

Not necessarily.

* The instructions that take long time to execute could be interrupted
in the middle. Such as chain operations or integer division.

* Reads and writes of the operands that are wider then the CPU bus (such
as 64-bit reads and writes) could be interrupted in between the bus cycles.

* Read/write bursts can be interrupted.

* Bus interface unit can shuffle the order of bus operations. In some
cases this could be not transparent to the CPU.

I never count on implicit atomicity of any operation.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com


From: Paul Keinanen on 3 Feb 2010 16:35
On Wed, 3 Feb 2010 11:04:10 -0800 (PST), Didi <dp(a)tgi-sci.com> wrote:

>In the context of a single bus master - the processor core - any
>instruction
>is atomic on all processors I know.

On a processor that supports virtual memory, each memory (byte)
reference might be interrupted.

For this reason, the hardware will often require that the interlocked
data is 32/64 bit aligned, in order to be atomic.


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