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From: Paul Keinanen on 4 Feb 2010 05:57
On Thu, 4 Feb 2010 03:57:53 +0000 (UTC), Przemek Klosowski
<przemek(a)tux.dot.org> wrote:

>On Wed, 03 Feb 2010 14:33:20 -0800, Didi wrote:
>
>>> I never count on implicit atomicity of any operation.
>>
>> Well neither do I, but things are not that bad. I have developed an
>> almost subconscious feeling when and what I need of that, so much so I
>> even forgot the obvious case of crossing page boundary
>
>Of course it depends on the architecture. One of the original design
>reasons for the RISC architectures was the unpredictability and complex
>behavior of long CISC instructions. VAX instruction set for instance
>allowed a single instruction that touched up to 52 (!!!) pages, with that
>many page faults being the worst case:
>
>http://pupgg.princeton.edu/cdrom12/html/ssb71/6258/6048p066.htm

Just wondering, how they have arrived at this figure. The character
string instructions can touch far more pages than that and those
instructions are definitely intended to be interruptible, by polluting
registers R0..R5, even if these registers are not referenced in the
instruction, in order to saving pointers and remaining counts at the
interrupt.

I tried to count the maximum number of page faults during operand
evaluation, before any character string or packed decimal access
starts and reached 20 pages on a six operand instruction (three
address+count pairs). This assumes indirect addressing on all
operands, in which each pointer is on a page boundary and the three
byte counts are on page boundaries too and of course the instruction
on a page boundary too (2+3x(2+4)) pages. Of course, more page faults
may occur, when the actual byte or packed decimal processing starts.

From: Robert Adsett on 4 Feb 2010 12:03
On Feb 3, 5:33 pm, Didi <d...(a)tgi-sci.com> wrote:
> On Feb 3, 9:56 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote:
>
> > Didi wrote:
> > > In the context of a single bus master - the processor core - any
> > > instruction is atomic on all processors I know.
>
> > Not necessarily.
>
> > * The instructions that take long time to execute could be interrupted
> > in the middle. Such as chain operations or integer division.
>
> Division? I have not seen that being interruptible. Where do they do
> that?

As I recall on the ST10/C167 both division ans multiplication
operations are interruptable. If you wish to use those operations
withing an interrupt you must store extra context.

Robert
From: Didi on 4 Feb 2010 15:13
On Feb 4, 7:03 pm, Robert Adsett <s...(a)aeolusdevelopment.com> wrote:
> On Feb 3, 5:33 pm, Didi <d...(a)tgi-sci.com> wrote:
>
> > On Feb 3, 9:56 pm, Vladimir Vassilevsky <nos...(a)nowhere.com> wrote:
>
> > > Didi wrote:
> > > > In the context of a single bus master - the processor core - any
> > > > instruction is atomic on all processors I know.
>
> > > Not necessarily.
>
> > > * The instructions that take long time to execute could be interrupted
> > > in the middle. Such as chain operations or integer division.
>
> > Division? I have not seen that being interruptible. Where do they do
> > that?
>
> As I recall on the ST10/C167 both division ans multiplication
> operations are interruptable.  If you wish to use those operations
> withing an interrupt you must store extra context.
>
> Robert

What a nightmare stack frame to handle... :-). On the TI 54xx division
not adding latency is solved in a very elegant way - it is done in a
loop by a "subtract conditionally" opcode (don't remember the exact
name, I wrote an assembler for it but that was almost 10 years ago).
Anyway, it uses the loop mode execution so in effect the division
is really fast - 16 cycles for 32/16 IIRC (or was it for 16/16) - but
interruptible with no horror stack frames.

Dimiter
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